Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword
Like this
1Activity
0 of .
Results for:
No results containing your search query
P. 1
A finite state machine

A finite state machine

Ratings: (0)|Views: 62 |Likes:
Published by santosh861986

More info:

Published by: santosh861986 on Jan 24, 2011
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as DOCX, PDF, TXT or read online from Scribd
See more
See less

01/24/2011

pdf

text

original

 
 A
finite state machine (FSM)
or simply a state machine, is a model of behavior composed of a finitenumber of states, transitions between those states, and actions.It is like a "flow graph" where we can seehow the logic runs when certain conditions are met.In this aricle I have implemented a
Mealy
type state machine in VHDL.The state machine bubblediagram in the below figure shows the operation of a four-state machine that reacts to a single input"input" as well as previous-state conditions.The code is given below:
library
 ieee; 
use
 IEEE.std_logic_1164.
all
; 
entity
mealy
is
 
 port
 (clk: 
in
 std_logic;  reset: 
in
 std_logic;  input: 
in
 std_logic;  output: 
out
 std_logic ); 
end 
mealy; 
architecture
behavioral
of
mealy
is
 
type
state_type
is
 (s0,s1,s2,s3); --type of state machine. 
signal
current_s,next_s:state_type; --current and next state declaration. 
 begin
 
 process
 (clk,reset) 
 begin
 
if
 (reset='1') 
then
 current_s <=s0; --default state on reset. 
elsif
 (
rising_edge
(clk)) 
then
 current_s <=next_s; --state change. 
end 
 
if
; 
end 
 
 process
; --state machine process. 

You're Reading a Free Preview

Download
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->