finite state machine (FSM)
or simply a state machine, is a model of behavior composed of a finitenumber of states, transitions between those states, and actions.It is like a "flow graph" where we can seehow the logic runs when certain conditions are met.In this aricle I have implemented a
type state machine in VHDL.The state machine bubblediagram in the below figure shows the operation of a four-state machine that reacts to a single input"input" as well as previous-state conditions.The code is given below:
(s0,s1,s2,s3); --type of state machine.
current_s,next_s:state_type; --current and next state
current_s <=s0; --default state on reset.
current_s <=next_s; --state change.
; --state machine process.