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Table Of Contents

1.1 Review of CMOS FET’s
1.2 Creating a New Library in Cadence
1.3 Schematic Capture
1.3.1 Virtuoso Schematic Editor
1.3.2 Virtuoso Symbol Editor
1.3.3 Affirma Analog Circuit Design Environment
1.3.4 The Waveform Window
1.3.5 The Cadence Calculator
1.4 Generating the Characteristic MOSFET Curves
1.4.1 N-channel Enhancement-Type MOSFET
1.4.2 P-channel Enhancement-Type MOSFET
An Introduction to Op-Amps
2.1 Parameters of an Op-Amp
2.1.1 Offset Voltage
2.1.2 Input Current
2.1.3 Input Common Mode Voltage Range
2.1.4 Maximum Output Voltage Swing
2.1.5 Output Impedance
2.1.6 Common-Mode Rejection Ratio
2.1.7 Supply Voltage Rejection Ratio
2.1.8 Slew Rate
2.1.9 Unity Gain Bandwidth and Phase Margin
2.1.10 Settling Time
2.2 Methodology of Choosing Op-Amp Parame-
2.3 How to Adjust the Parameters
2.3.1 Specification
2.3.2 Procedure of Optimization
2.3.3 Optimize the Parameters of the Op-Amp
2.3.4 How to get the Quiescent point in a complex circuit
2.4 Target Op-Amp Specifications
3.1 Ideal Characteristics of a Current Mirror
3.2 Basic Current Mirror Derivation
3.3 Benchmark Test Circuit
3.4.2 Cascade/Cascode Current Mirror
3.4.3 Wilson Current Mirror
3.4.4 Modified Wilson Current Mirror
3.4.5 Reduced Cascade Current Mirror
3.5 Conclusion
Differential Input Stage
4.1 The Unbuffered Op-Amp
2. Differential input stage
4.2 Small Signal Equivalent Circuits
4.3 The Frequency Response
4.4 Phase Margin
4.5 Compensation
4.6 Adding Rz in series with Cc
4.7 Gain Bandwidth Product
4.8 Large Signal Consideration
4.9 Slew Rate
4.10 The Common-Mode Range
4.11 Important Relationships for The Design
4.12 Tradeoffs for Increasing the Gain of the Two
4.13 Design Methodology for the Two Stage Op-
4.14 Design Example
4.15 Limitations of the Two Stage Op-Amp
4.16 The Cascode Op-Amp
Inverting Amplifiers
5.1 Inverter with Active Resistor Load
5.2 Inverter with Current Source/Sink Load
5.3 Push-Pull Inverter
5.4 Comparison
5.5 Application
6.2 Class-A Output Stage
6.2.2 Common-Drain (Source-Follower) Output Amplifier
6.2.3 Power Analysis
6.3 Class-B Output Stage
6.3.1 Push-Pull, Inverting CMOS amplifier
6.3.2 Power Analysis
6.4 Class-AB Output Stage
6.6 Conclusion
6.7 Design Considerations
6.7.1 Negative Feedback
6.7.2 Frequency Compensation
Integrating the Sub-Circuits
7.1 Overall Performance
7.2 The Measurement of Some Main Parameters
7.2.1 Input Offset Voltage
7.2.2 Common-Mode Rejection Ratio (CMRR)
7.2.3 Output Resistance - Ro
7.3 Delivering Power to the Load/Instantaneous
7.4 Improving the Output Buffer
7.4.1 Stabilizing the Output
7.4.2 The Final Schematic
Closing Remarks
8.1 Conclusion
8.2 Future Work
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Cadence OpAmp Schematic Design Tutorial

Cadence OpAmp Schematic Design Tutorial

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Published by simbarry

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Published by: simbarry on Jan 31, 2011
Copyright:Attribution Non-commercial


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