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Table Of Contents

STATEMENT OF ORIGINAL AUTHORSHIP
1.1 Description of a Digital Fibre-Optic Link system
1.2 Aims
1.3 Overview of the thesis
2.1 Overview of Optic Link Design
2.1.1 Link Design
2.2 Optical Source
2.2.1 Comparison between LED and Laser Diode
Table 1: Comparison of LED and LD [3]
2.2.2 LED
2.3 Advantages of fibre-optic communications [1]
2.4 Optical Module
2.4.1 Optical transmitter [5]
2.4.2 Optical receiver [5]
2.4.3 Optical cable
2.5 Power Budget
2.6 Rise time budget
3.1 Overview
3.2 Hardware Implementation
3.2.1 Optical Module (Transmitter/Receiver circuitry)
3.3 Power Measurement
3.3.1 Overview
3.3.2 Attenuation [6]
3.3.3 Bending Loss [6]
3.3.4 Mechanical Misalignment
3.4 Jitter Testing
3.4.1 Concept of Jitter
3.4.2 Implementation of Jitter
3.5 USB Module
3.5.1 Overview
3.5.2 Concept of transmitter link
3.5.3 Concept of receiver link
3.6 Method of Transmission
3.6.1 Line Coding [1]
Figure 20: RZ Modulation
3.6.2 Data coding
3.6.3 Data communication scheme
3.6.4 Asynchronous Transmission
3.6.5 Synchronous Transmission
3.6.4 Parallel to Serial Conversion
3.6.5 SHIFT REGISTERS
3.6.6 Serial and Parallel Transfers and Conversion
3.7 NRZ/RZ Circuit Design
3.7.1 RZ transmitter module
3.7.2 Multiplier Circuit
3.7.3 Return-Zero receiver module
3.7.4 Software Testing
3.7.5 Hardware Testing
Figure 37: Illustration of Hardware testing circuit
4.1 Overview of Software Design
4.2 BER (Bit-Error-Ratio)
4.2.1 Bit Error Ratio
4.2.2 Bit Error Ratio Tester [12]
4.3 Pseudo Random Generator
4.3.1 Concept
4.4 Eye diagram
4.4.1 Concept
Figure 43: Concept of an eye diagram [12]
4.4.2 Setup of Eye diagram [16]
4.5 Mask measurement
Chapter 5: Presentation and Discussion of Results
5.1 Overview of This Chapter
5.2 Power Measurement Results
5.3 Jitter Results
6.1 Further Development
References
Appendix A – Results and Simulations
Power measurement
Table A-1: Output Power (dBm) vs. NRZ/RZ (No. of Bits)
Figure A-2: No. of bit errors against Receiver Input Power
Table A-5: Bending Radius measurement data
Jitter Measurement (Eye diagram)
Figure A-7: 0.23% Jitter
Figure A-8: 0.3% Jitter
Appendix B –Flowchart of Software Implementation
Figure B-9: Attenuation Help Menu
Appendix C – Schematic Drawing
Figure C-1: PCB of RZ-Transmitter
Figure C-2: Schematic of Return-Zero module (Receiver)
Figure C-5: Simulated VPI BER vs Received Power
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Published by: terminatetushar on Feb 01, 2011
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