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Table Of Contents

ACKNOWLEDGMENTS
ABSTRACT
CHAPTER 1 :INTRODUCTION
1.1 Problem Definition
1.3 Phase Locked Loop Fundamentals
Figure 1-1: Basic pll block diagram
1.3.1 Loop Filter
1.3.2 Frequency Synthesizer
Figure 1-2 Basic frequency Synthesizer
1.4 Applications of PLL
1.5 Classification of PLLs
1.6 Goal
1.7 Thesis Organization
CHAPTER 2 : A BRIEF REVIEW OF PREVIOUS WORK
1.8 Background
Figure 2-3 Conventional PLL Block Diagram
1.9 Phase Detector
1.10 Voltage-Controlled Oscillator
1.11 Loop Filter
Figure 2-6:Figure (a) Passive filter (b) Active Filter
Figure 2-7: Ranges of the dynamic limit of a PLL
1.12 Configuration of PLL Application
Figure 2-8:Synthesizer PLL
1.13 Analog , Digital, and Hybrid PLL’S
1.14 Popular PLL Integrated Circuits (IC’s)
CHAPTER 3 : PROPOSED APPROACH AND IMPLEMENTATION
1.15 Architecture of proposed PLL
Figure 3-9: Block diagram of the proposed PLL
1.16 Phase Frequency Detector
1.16.1 Conventional Phase Detector
Figure 3-11: Phase detector using TSPC type D flip flop
1.16.2 Phase Detector Incorporated in Proposed PLL
Figure 3-12:Phase Frequency Detector
1.16.3 Simulation Output and Results of Incorporated Phase Frequency Detector
Figure 3-13 : when Vref is leading Fout
Figure 3-14: when Vref is lagging Fout
Figure 3-15:when Vref is exactly in phase with Fout
1.17 Charge Pump and Loop Filter
1.17.1 Conventional Charge Pump
Figure 3-16: when Vref is exactly in phase with Fout
Figure 3-17:Conventional Charge pump
1.17.2 Charge pump incorporated in the proposed PLL
Figure 3-18:Proposed charge pump circuit
Figure 3-19: Bias generator used in the charge pump
Figure 3-20:The output of control voltage when up signal got activated
1.19 Voltage Controlled Oscillator (VCO)
1.19.1 The most important specifications of the VCO
1.19.2 Ring oscillator architecture
Figure 3-24:Basic structure of the ring oscillator
Figure 3-25: problem of insufficient gain
Figure 3-26: delay stage cell schematic in VCO
Figure 3-27: Load used in proposed ring oscillator showing inductive impedance
1.19.3 High speed ring oscillator with dual delay paths
Figure 3-29:ring oscillator structure with dual delay paths
1.20 Frequency Divider
1.20.1 Digital dividers
Figure 3-31: output waveforms of the VCO for different control voltage
Figure 3-32: Divide by 2 frequency divider output
Figure 3-34: Proposed 6 bit frequency divider
Figure 3-35:Output waveforms of the frequency divider
CHAPTER 4 : SIMULATION RESULTS
CHAPTER 5 :CONCLUSION AND FUTURE SCOPE
REFERENCES
GLOSSARY OF TERMS USED
CHECKLIST
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Bharat_MS__DISSERTATION_BITS_PLL_2008HB99501

Bharat_MS__DISSERTATION_BITS_PLL_2008HB99501

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Published by: bharatroonwal on Feb 05, 2011
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11/14/2012

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