Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword or section
Like this
4Activity

Table Of Contents

•Industry and Product Overview
Industry and Product Overview
System Generator
System Level Modeling with System Generator
The System Generator Design Flow
Arithmetic Data Types
Hardware Handshaking
Multirate Systems
Bit-True and Cycle-True Modeling
Automatic Testbench Generation
•What is a Xilinx Block?
What is a Xilinx Block?
Instantiating Xilinx Blocks within a Simulink Model
The Block Parameters Dialog Box
The Nature of Signals in the Xilinx Blockset
Use of Xilinx Smart-IP Cores by the System Generator
Licensed Cores
Common Options in Block Parameters Dialog Box
Arithmetic Type
Implement with Xilinx Smart-IP™Core (if possible)
Generate Core
Latency
Precision
Number of Bits
Overflow and Quantization
Override with Doubles
Sample Period
Basic Elements
Addressable Shift Register
Black Box
Concat
Constant
Convert
Counter
Delay
Down Sample
Get Valid Bit
Parallel to Serial
Register
Reinterpret
Serial to Parallel
Set Valid Bit
Slice
Sync
Up Sample
Communication
Convolutional Encoder
Depuncture
Interleaver Deinterleaver
Puncture
RS Decoder
RS Encoder
Viterbi Decoder
Math
Accumulator
AddSub
CMult
Inverter
Logical
Mult
Negate
Relational
Scale
Shift
SineCosine
Threshold
MATLAB I/O
Gateway Blocks
Enabled Subsystems
Gateway In
Gateway Out
Quantization Error Blocks
Display
Memory
Dual Port RAM
FIFO
Single Port RAM
State Machine
Mealy State Machine
Moore State Machine
Registered Mealy State Machine
Registered Moore State Machine
•Using the System Generator installer
Using the System Generator installer
Uninstalling previous System Generator directories
Installed System Generator directory
Using Black Boxes
Black Box window
Use of mixed language projects
Incorporating mixed language black boxes
Tips for creating a high performance design
Using the System Generator Constraints Files
System Clock Period
Multicycle Path Constraints
IOB Timing and Placement Constraints
Example for showing constraints use
Important Issues
Files automatically created by System Generator
•Xilinx ISE 4.1i Project Navigator
Xilinx ISE 4.1i Project Navigator
Opening a System Generator project
Customizing your System Generator project
Implementing your design
Simulating using ModelSim within the Project Navigator
Using an EDIF software flow
Simulation
Compiling your IP
Associating ModelSim with ISE 4.1i Project Navigator
Xilinx software tools resources
Demonstration designs
Perl scripts
0 of .
Results for:
No results containing your search query
P. 1
xilinx_ref_guide

xilinx_ref_guide

Ratings: (0)|Views: 397|Likes:
Published by amol771986

More info:

Published by: amol771986 on Feb 11, 2011
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

12/18/2012

pdf

text

original

You're Reading a Free Preview
Pages 4 to 22 are not shown in this preview.
You're Reading a Free Preview
Pages 26 to 86 are not shown in this preview.
You're Reading a Free Preview
Pages 90 to 118 are not shown in this preview.
You're Reading a Free Preview
Pages 122 to 148 are not shown in this preview.

Activity (4)

You've already reviewed this. Edit your review.
1 thousand reads
1 hundred reads
Rachid Labidi liked this
RayzonExpress liked this

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->