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r05311403 Switching Theory and Logic Design

r05311403 Switching Theory and Logic Design

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Published by: SRINIVASA RAO GANTA on Aug 21, 2008
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Code No: R05311403
Set No. 1
III B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1. (a) Explain di\ufb00erent methods used to represent negative numbers in binary sys-
tem.
[6]
(b) Perform the subtraction with the following unsigned binary numbers by taking
the 2\u2019s complement of the subtrahend.
[5\u00d72 = 10]
i. 11010 - 10110

ii. 11011 - 1001
iii. 100 - 110100
iv. 1010101 - 1010101

v. 11 - 1101
2. (a) Express the following functions in sum of minterms and product of maxterms.
[8]
i. (xy + z) ( y + xz)
ii. B\u2019D + A\u2019D + BD
(b) Obtain the complement of the following Boolean expressions.
[8]
i. AB\u2019C + AB\u2019D + A\u2019B\u2019

ii. A\u2019B\u2019C + ABC? + A\u2019B\u2019C\u2019D
iii. ABCD + ABC\u2019D\u2019 + A\u2019B\u2019CD
iv. AB + ABC\u2019

3. (a) Di\ufb00erentiate prime implicant and non prime implicant, essential prime impli-
cant and non essential prime implicant.
[8]
(b) Reduce the following function using K- map and identify prime implicants and
essential prime implicants F=
\ue000
m(0,1,2,3,6,7,13,15)
[8]
4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates.
(b) Draw the logic diagram of a single bit comparator.
[12+6]
5. Write a brief note on:
(a) Architecture of PLDs
(b) Capabitation and the limitations of threshold gates.
[8+8]
6. (a) Compare synchronous & Asynchronous circuits
(b) Design a Mod-6 synchronous counter using J-K \ufb02ip \ufb02ops.
[6+10]
1 of 2
Code No: R05311403
Set No. 1
7. (a) Convert the given Mealy machine to Moore Machine.
Present State Next State
Output
x=0
x=1
P
R,0
Q, 0
Q
P,1
S,0
R
Q,1
P,1
S
S,1
R,0
(b) Give the state diagram of a binary serial adder and design the circuit for carry
output using D - \ufb02ip-\ufb02op.
[8+8]
8. For the ASM chart given 8:
Figure 8
(a) Draw the state diagram.
(b) Design the control unit using D \ufb02ip-\ufb02ops and a decoder.
[8+8]
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
2 of 2
Code No: R05311403
Set No. 2
III B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1. Convert the following to Decimal and then to Binary.
(a) 101116
(b)ABCD16

(c) 72348
(d) 77668
(e) 12810

(f) 72010.
[3+3+3+3+2+2]
2. (a) Draw the NAND logic diagram that implements the complement of the fol-
lowing function.
[8]
F(A,B,C,D) = \u03a3 (0,1,2,3,4,8,9,12)
(b) Obtain the complement of the following Boolean expressions.
i. AB + A(B + C) + B\u2019(B + D)
ii. A + B + A\u2019B\u2019C
[4]
(c) Obtain the dual of the following Boolean expressions.
i. A\u2019B + A\u2019BC\u2019 + A\u2019BCD + A\u2019BC\u2019D\u2019E
ii. ABEF + ABE\u2019F\u2019 + A\u2019B\u2019EF
[4]
3. Apply Branching method to simplify the following function
F (A, B, C, D) =
\ue000
M(0,1,4,5,9,11,13,15,16,17,25,27,28,29,31)d(20,21,22,30).
[16]
4. (a) Realize Full Adder Using two half adders and logic gates.
(b) Draw the block diagram of BCD adder using two 4-bit parallel binary adders
and logic gates.
[4+12]
5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit.
[8+8]
1 of 2

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