VHDL LAB MANUAL

Starting With XILINX Tool for Chip Designing and simulation

Design requirements:
Design of ANDGate. The pin definitions and numbers are shown in the
functional logic diagram as shown in below figure.

Functional Logic Diagram

a (in)
c (out)
AND
b(in)
b(in) Gate

Using the Design Software

Starting the ISE7.1 Project Navigator

Look for the Xilinx Icon and double click on it.

Using the Xilinx ISE7.1 Project Navigator.

The Xilinx Design System is the tool we will use to write our VHDL code and/or
to draw our schematics and simulate them electronically. If we draw a
schematic, the schematic program will generate a VHDL program that includes
all the information in our schematic.
In order to use our Xilinx software and Xilinx FPGA chip, all of our designs
must be made with parts that Xilinx Design Manager recognizes. These parts
are the parts which are included in the Xilinx library.

Department of Electronics & Communication 1

VHDL LAB MANUAL

Click on OK.

Department of Electronics & Communication 2

VHDL LAB MANUAL

Write and Compile VHDL program

• To define your design using VHDL you will have to create a new VHDL
source. To do this, select Project→New Source… and select VHDL
Module.

• A VHDL source file is created and opened in the edit/view window on the
right-hand side of the project navigator. You can now write your VHDL
program for the design. Once completed, save the program.

Once the VHDL program is completed, select Synthesize from the

Processes window. Repair any syntax errors and repeat until the
program compiles without errors or warnings.

Department of Electronics & Communication 3

VHDL LAB MANUAL

Building a Circuit

To build a schematic in Xilinx:

• Open a new project by selecting New Project... from the File menu.
This will pop up the window shown in Figure: New Project

• Give your project a name and location, the Device Family, the Device,
the Package, and the Speed Grade. Make sure the Design Flow is
XST VHDL… as shown in the subsequent screen shots. Then click
FINISH.

Department of Electronics & Communication 4

VHDL LAB MANUAL

Department of Electronics & Communication 5

VHDL LAB MANUAL

Department of Electronics & Communication 6

VHDL LAB MANUAL

The above steps will create a .ise folder which can be used as a skeleton for
any program to be written using VHDL\Verilog for chip designing, as shown
in the screen shot below.

Department of Electronics & Communication 7

VHDL LAB MANUAL

Follow the steps as shown below, to create a New source for appropriate
design method to be used, i.e VHDL module\ Verilog module \ Test bench
etc… Also specify the file name for the same, and click NEXT.

Department of Electronics & Communication 8

VHDL LAB MANUAL

Specify the Entity and Architecture Name used for design then click NEXT
and FINISH.

Department of Electronics & Communication 9

VHDL LAB MANUAL

Space for writing code will be created, with some architecture and library
level coded lines generated automatically.

Department of Electronics & Communication 10

VHDL LAB MANUAL

Declare the variables for input, output or inout ports as required for the
functional block within entity using PORT declaration syntax.
Write necessary code within Architecture declaration.
Points to remember:
• A design will have only one entity declaration and more than one
architecture body for an entity.
• Entity Declaration includes: Port names and indicates whether they are
input, output or in-out ports and also specifies data-type for example: BIT,
STD_LOGIC, Integer etc.
Exa: Entity (
I1: IN std_logic;
O1: OUT std_logic
);

I1, O1: port names

In, Out: Mode
std_logic: data-type
• Architecture declaration: There are three ways of declaring an
architecture, they are a) Structural (Component instantiation) b) Data flow
and c) Behavioral.
Signals and component instantiation are declared inside the architecture
(before Keyword Begin of Architecture).
Variables are declared inside the Process statements (don’t declare
signals inside the process).

Department of Electronics & Communication 11

VHDL LAB MANUAL

Department of Electronics & Communication 12

VHDL LAB MANUAL

To ensure the code is syntactically correct click on Synthesize-XST or

Check syntax in Process View Window as shown below...

Department of Electronics & Communication 13

VHDL LAB MANUAL

Save the file or else pop-up as shown below will be displayed. If so click on
YES to save it.

Department of Electronics & Communication 14

VHDL LAB MANUAL

If syntactically correct all the options will be checked in GREEN as shown

below.

Department of Electronics & Communication 15

VHDL LAB MANUAL

Simulation
ModelSim is used to simulate the schematics made in Xilinx. This makes it
possible to simulate your design in Xilinx to verify its operation. You may do
so once your circuit is constructed by the following steps:
1.In Project Navigator highlight the schematic you want to simulate.
2. Double click on Launch ModelSim Simulator from the Xilinx Project
Navigator Window as seen in Figure

Department of Electronics & Communication 16

VHDL LAB MANUAL

The following window will be displayed in MODELSIM simulator with

corresponding I/O Ports as declared within Entity

Department of Electronics & Communication 17

VHDL LAB MANUAL

Follow the steps as shown to provide values for the input ports in order to
simulate the design.

Department of Electronics & Communication 18

VHDL LAB MANUAL

Department of Electronics & Communication 19

VHDL LAB MANUAL

Check the waveforms created.

Department of Electronics & Communication 20

VHDL LAB MANUAL

Department of Electronics & Communication 21

VHDL LAB MANUAL

OR

Starting the MODELSIM XE

Look for the ModelSim Icon and double click on it.

The following window will be displayed..

Department of Electronics & Communication 22

VHDL LAB MANUAL

First make a do file.

Right click File Menu and open the existing AndGate source where you saved.

Department of Electronics & Communication 23

VHDL LAB MANUAL

Department of Electronics & Communication 24

VHDL LAB MANUAL

Corresponding .vhd file will be opened.

Department of Electronics & Communication 25

VHDL LAB MANUAL

Compile the code using Compile in Menu bar.

Department of Electronics & Communication 26

VHDL LAB MANUAL

Department of Electronics & Communication 27

VHDL LAB MANUAL

Click Compile then Done to close the compilation window.

Department of Electronics & Communication 28

VHDL LAB MANUAL

To simulate the design, select work\ filename.vhd in the library window and
select simulate option by right clicking on the filename.

Following window will be displayed..

Department of Electronics & Communication 29

VHDL LAB MANUAL

#Kill old simulation if running

quit -sim
#Start a new one
AndGate/Simulate
#Bring up the waves window using
viewwave option in Menu bar
#Put signals of interest in waves window
add wave InputA
add wave InputB
add wave OutputC
#set the data input signals
#force is to make sure that what you put over-rides anything else
#0, 1 10ns -r 20ns means force to 0 for 10ns then force to 1, repeat every
20ns
force InputA 0, 1 10ns -r 20ns
force InputB 0, 1 20ns -r 40ns
force InputC 0, 1 10ns -r 20ns
force InputD 0, 1 20ns -r 40ns
run 160ns

Department of Electronics & Communication 30

VHDL LAB MANUAL

Department of Electronics & Communication 31

VHDL LAB MANUAL

Department of Electronics & Communication 32

VHDL LAB MANUAL

Department of Electronics & Communication 33

VHDL LAB MANUAL

Department of Electronics & Communication 34

VHDL LAB MANUAL

Department of Electronics & Communication 35

VHDL LAB MANUAL

Department of Electronics & Communication 36

VHDL LAB MANUAL

Department of Electronics & Communication 37

VHDL LAB MANUAL

There are various options on running a simulation. The Run toolbar is shown
below.

Restart-This resets the simulation and reassigns all of the inputs and outputs
to U.
Run-Run will cause the simulation to run for the designated about of
picoseconds as shown above.
Continue Run-This is used to restart simulation after breaking or stopping a
simulation.
Run All- This will cause the simulation to go on forever. You must click the
break button to stop it at some point.
Break- Used to stop a simulation from running.

Here are some keyboard shortcuts that may be useful while in the Wave
window:

Zoom In- i I or +
Zoom Out- o O or -
Zoom Full- f or F
Zoom Last- l or L
Zoom Range- r or R
Next Transition- tab

Department of Electronics & Communication 38

VHDL LAB MANUAL

For generating program file select Generate Programming File option in

Process View Window.

Department of Electronics & Communication 39

VHDL LAB MANUAL

Department of Electronics & Communication 40

VHDL LAB MANUAL

Create Constraints File and Define Pin Assignments . Select the Assign
Package Pins and assign the pins as follows:

Signal Pins XSA Function NAme

a 48 DIPSW4(DIPSWID)
b 51 DIPSW3(DIPSWIC)
c 2 LED – S1

To assign the pins, enter the pin number (with a preceding p) in the Design
Object List – I/O Pins window. Once the pins are assigned the window
should look like the following figure:

Pin Assignment Image

Design Object List – I/O Pins

I/O Name I/O LOC Function Macroloc
Directions Block
c Output P2
a Input P48
b Input P51
It is very important to save and close the pin assignment window before
proceeding to the next step. Otherwise your pin assignments may not be
assigned correctly.

Select Assign Pin Package option in Process View window to do pin

assignment as discussed above.

Department of Electronics & Communication 41

VHDL LAB MANUAL

Department of Electronics & Communication 42

VHDL LAB MANUAL

To view RTL schematic of the functional block Run RTL Schematic in

Process View window.

Department of Electronics & Communication 43

VHDL LAB MANUAL

The corresponding RTL level block will be displayed as shown which indicates
input and output of the block.

Department of Electronics & Communication 44

VHDL LAB MANUAL

To view internal description of the block click on the RTL block then following
structure will be displayed.

Department of Electronics & Communication 45

VHDL LAB MANUAL

To view the process technology Run View Technology Schematic in

Process View window.

Department of Electronics & Communication 46

VHDL LAB MANUAL

Department of Electronics & Communication 47

VHDL LAB MANUAL

Department of Electronics & Communication 48