Professional Documents
Culture Documents
for higher operating speeds and device packing densities. The circuits fabricated
on bulk Si wafer could not satisfy these requirements. The present paper seeks to
a novel technology using atomic layer cleavage, which allows SOI processing to
be available for many substrate materials. It also presents various other fabrication
methods for SOI technology. Using the same transistor dimensions, SOI’s global
direct transistor scaling through reduction in the wafer area needed for the device
isolation. The SOI process exploits Nano cleaving, which reduces cost and creates
SOI wafers with exceptional material quality and high yield. Nano cleave is
This paper encompasses Nano cleave process fabrication steps in a lucid manner.
ABSTRACT
AABSTRACT
A
1. PREAMBLE
Silicon-on-insulator (SOI) technology provides opportunities to increase
transistor switching and at the same time to improve performance for low-power, battery-
driven electronics. With its ability to increase device density through reduction in
isolation area, SOI can postpone the need to shift to smaller scale transistors. SOI can
contribute to reduced manufacturing costs by simplifying IC fabrication processes,
through the elimi-nation of high-energy implantation for well doping and simplification
of device isolation. SOI also provides opportunities beyond conventional semiconductor
devices. SOI is a key method for fabricating “Silicon-on-Anything” devices, which have
the potential to integrate communications, smart cards, sensors and displays with
portable, low-power memory and logic devices, as in Figure 1.
Using the same transistor dimensions, SOI’s global dielectric isolation enables IC
manufacturers to pack more die on a wafer without direct transistor scaling, through
reduction in the wafer area needed for device isolation, as shown in Figure 2. This
increase in the die per wafer yield is especially valuable in logic and I/O-dominated
layouts such as in system-on-a-chip (SOC) devices. In addition to speed gains in
mainstream applications, the negligible current leakage and lower power requirements of
SOI-based chips can dramatically improve the performance of battery-powered
communication and computing devices for mobile electronics.
3. SOI: AN EMERGING MARKET FOR GIGAHERTZ-SPEED, LOW POWER
DEVICES
The need for lower cost IC devices which operate in the Gigahertz frequency
range used for mobile communications is driving the switch to SOI wafers. Broadband
communication networks, operating on battery or solar cell power, need the low-power,
small die size and global Isolation of SOI designs. The lower cost of Silicon device
processing on large area wafers provides a key advantage for SOI over communication
and computing devices fabricated with more exotic materials, such as GaAs.
Today’s standard processes fabricate transistors directly onto a bulk silicon wafer
surface. These transistors operate at relatively low switching speed because large
volumes of semiconductor material require more energy to turn on and off. For SOI-
based processes, transistors are built on a thin silicon surface layer isolated from the
wafer by a layer of oxide, and chips run 20% to 35% faster because less charge is needed
to switch the transistor state. This speed gain is equivalent to the advantage gained by a
full generation of device scaling on bulk-Silicon.
1. Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee,Kang-Min Lee, Tae-
Hum Yang, Jin-Yong Jung and Hoi-Jun Yoo, “A Reconfigurable Multilevel
ParallelGraphics Memory with 75GB/s Parallel Cache Replacement Bandwidth”,
Symposium on VLSI Circuits 2001, C21p3, in press, Jun. 2001.
3. J.Kook, et al, “A Low Power Reconfigurable I/O DRAM Macro with Single Bit line
Writing Scheme”, 26th European Solid-State Circuits Conference, pp.384-387,Sept.,
2000.