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Implementation and Design of CPLD-Based

Implementation and Design of CPLD-Based

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Implementation
and
Design
of
CPLD-Based
Switched-Capacitor
Step-Down
DC-DC
Converter
with
Multiple
Output
Choice
Yuen-Haw
Chang
Department
and
Graduate
Institute
of
Computer
Science
and
Information
Engineering,
Chaoyang
University
ofTechnology,Taichung,
Taiwan,
R.O.C.Abstract--A
simple
quasi-switched-capacitor
(QSC)
step-
down
DC-DC
converter
with
multipleoutput
choice
(9V/5V,9V/3.3V,
9V12V)
is
designed
andimplemented
via
complex-
programmable-logic-device-based
(CPLD)
digital
controller
for
low-power
applications
(Input:
7.0-9.OV,
load:
50-4000hms).
The
integrated
digital
controller
is
implementedby
combinationwith
Verilog
CPLD
and
ADC/DAC
chips
to
achieve
theclosed-
loop
control
of
QSC
converter.
Such
a
Verilog-based
CPLD
can
make
controller
design
more
flexible,
simple
and
reliable.
In
fact,
SC
circuit
needs
no
inductive
element,
so
I.C.
fabrication
is
promising,
and
it
is
prettysuitable
for
low-power
VLSI
applications.
An
interleaved
current-mode
control
is
employed
here
from
battery
source
interleaved
charging
to
the
series
capacitors
of
different
cells
by
a
voltage-controlled
current
source,so
the
continuousinput
current
comes
into
being,
and
it
resultsin
a
good
feature:
low
electromagnetic
interference
(EMI).
Such
a
current-mode
control
is
able
to
not
only
enhance
output
robustnessagainstsource
variation/noise,
but
also
keep
regulation
capability
of
converter
with
loading
variation.Finally,
the
hardware
experiments
are
illustrated
to
show
the
efficacy
of
the
scheme
designed,
wheresome
topics
include:
voltage
conversion
and
outputripplepercentage,outputrobustness
against
source
variation,
and
regulation
capability
of
converter
with
loading
variation.
Index
Terms--quasi-switched-capacitor,
step-down,
DC-DC
converter,
Verilog-code,
CPLD.
I.
INTRODUCTION
In
recent
years,
due
to
the
popularity
of
potable
electronic
equipments,
for
example,
PDA,
notebook,
cellular
phone,
digital
camera,
pager,
and
e-book
...
etc.,
their
DC-DC
power
module
always
asks
for
some
good
features
of
small
volume,
light
weight,
high
power
density
and
efficiency,
and
good
regulation
capability.
Besides,
to
fit
in
with
requirements
of
various
functions
all
in
one,
both
multiple
output
choice
and
flexible
controller
design
become
essential
to
power
module
design
gradually.
Therefore,
more
manufactures
and
researchers
pay
much
attention
to
this
topic
on
development
of
a
more
flexible
power
converter
for
low-
power
applications,
ultimatelyrequiring
DC-DC
converters
realized
on
a
chip
bymixed
analog
VLSI
technology.
In
1996,
Chung
and
loinovici
suggested
a
completely
new
converter
scheme,
called
quasi-switched-capacitor
(QSC)
step-down
converter,
employedby
current-mode
controlidea
[1].
Basically,
this
converter
configuration
is
composed
of
two
SC
cells
working
in
anti-phase
periods.
In
fact,
this
configuration
is
almost
similar
to
that
of
Cheong's
[2],
but
the
most
different
point
between
them
is
to
use
aconstant
current
source
for
charging
capacitors(current-mode),
not
to
use
aconstant
voltage
source
(voltage-mode).
Here,
some
MOSFETS
are
operated
in
pinch-offregion
as
a
voltage-controlled
current
source,
so
the
capacitor
voltage
is
linearly
changed
with
time,
not
exponentially
charged
as
[2].
Thus,
the
input
current
is
continuous
and
constant,
but
not
discontinuous
and
variant
as
[2],
so
EMI
problem
can
beimproved.
From
1999,
researchers
are
concentrated
mainly
in
regulation
improvementand
capability
enhancement
of
the
QSC
converter
[3]-[8].
Henry
suggested
a
multi-stage
design
of
QSC
DC-DC
converter
for
improving
voltage
regulation
and
currentdrive
capability
[3].
For
step-down
design,
n
capacitors
are
discharged
in
parallel,
and
then
thelarger
outputcurrent
can
be
generated
for
the
heavierload
drive
[4].
For
step-up
design,
n
capacitors
are
discharged
in
series
for
supplying
the
higher
voltage
load
[5].
However,
someimprovement
spaces
still
exist,
for
example,
multiple
output
choice,
controller
reliability,
and
controller
design
flexibility.In
this
paper,
based
on
the
CPLD-based
digitalcontroller,a
simple
QSC
step-
down
DC-DC
converter
with
multiple
output
choice
is
implemented
for
a
variety
of
low-power
output.
Such
a
Verilog-code-based
CPLD
chip
can
make
controller
design
more
flexible,
simple,
and
reliable.
II.
CONFIGURATION
OF
CPLD-BAsED
CONVERTER
Inthis
section,
an
overall
circuit
configuration
of
CPLD-based
QSC
step-down
DC-DC
converter
is
suggested,
and
then
the
relative
power-part
circuit:
QSC
step-down
converter
is
introduced,
including:basic
control
operation
and
circuit
formulation.
2.1
CPLD-BASED
QSC
CONVERTERSCHEME
Fig.
1
shows
the
overall
circuit
configuration
of
CPLD-
based
QSC
step-down
DC-DC
converter,
and
it
contains
two
parts:
"power
part"
and
"controlpart"
for
achieving
the
closed-loop
control
of
QSC
converter
with
multiple
output
choice.
First,
the
above
half
of
Fig.
1
deals
with
the
power
part:
QSC
step-down
DC-DC
converter,
which
is
composed
of
capacitors
and
MOSFETS
as
shown
in
Fig.2
[1].
The
basic
control
operation
is
described
as
follows.
In
the
first
half-cycle,
let
QSA
operate
in
pinch-offregion
as
a
constant
controlled
current
source,
turnoff
SA
and
QSB,
and
turn
on
SB
in
triode
region
as
a
small
resistor.
Thus,
all
capacitors
of
cell
A
are
linearly
charged
by
the
constant
current
source.
At
the
same
time,
all
capacitors
of
cell
B
are
discharged
to
supply
the
load
RL
.
Based
on
the
same
idea,
in
the
second
half-cycle,
exchange
the
works
of
two
cells,
and
then
run
the
operation
cyclically.
1-4244-0844-X/07/$20.00
©2007
IEEE.
1651
 
IQSA
C
TS
TS
/2
Ts
/2
ISA
{
\
IQE
IST
[---l
0
1
-_
1
3B
I
cell
AT
'c.ell
B
]ID
n
Fig.
1
CPLD-based
QSC
step-down
converter
scheme
I
Cell
A
Charging
Dis
charging
ChargingDischargingCharging
Cell
s
Dischargig
Charging
Discharging
ChargingDischarging
Fig.2
Power-Part:
QSC
Step-Down
Converter
Thus,
it
is
obvious
that
the
output
vo
can
be
regulated
relative
to
how
much
thecapacitors
are
charged
by
controlled
current
source.
Fig.3
shows
the
theoretical
current
waveforms
of
this
QSC
converter.
Secondly,
the
control
part:
CPLD-based
digital
controller
is
shown
in
Fig.
1
below,
which
is
composed
of
Verilog-code-based
CPLD,
ADC/DAC
chips,
crystal
oscillator,
and
low-pass
filter.
From
the
view
of
controller
signalflow,
the
feedback
signal
of
the
converter:
output
vo
is
sent
into
the
OP-amp
low-pass
filter
for
high-
frequency
noise
rejection,
and
next
the
filtered
signal
is
transferred
into
the
digital
form
by
an
ADC
chip.
Then,
the
filtered/digitalized
output
is
sent
into
the
CPLD
chip,
and
then
compared
with
thedesiredoutputreference
(selected
by
the
multiple
output
choice)
to
produce
the
digital-form
control
signal
VGS.
Next,
with
the
DAC
chips,
this
digital-form
control
signal
VGS
is
transferred
back
into
the
analog
form,
and
then
to
adjust
thedrain
current
iD
(IQSA/IQSB
of
QSA/QSB)
for
the
capacitor
voltage
regulation
of
two
cells.
So,
the
Verilog-code-
based
CPLD
chiphastwo
tasks
to
do:
(1).
the
dynamic
production
of
the
digital-form
control
signal
VGS
according
to
both
the
filtered/digitalized
output
and
the
desired
output
reference,
and
(2).
the
static
generation
ofthe
timing-control
signalsof
QSC
converter
cells
according
to
the
scheduled
operation
of
Fig.3.
Here,
by
usingVerilog
programming,
the
CPLD-based
digital
Fig.3
Theoretical
current
waveform
controller
has
a
more
flexible,
simple
and
reliable
design
process
for
multiple
output
choice.2.2
FORMULATION
OF
QSC
STEP-DowN
CONVERTER
By
increasing
the
number
of
capacitors
of
two
cellsin
Fig.2,
a
circuit
configuration
of
n-stage
QSC
step-down
DC-DC
converter
is
suggested
as
shown
in
Fig.4
to
supply
theload
RL
from
the
source
Vs.
This
n-stage
QSC
converter
is
still
composed
of
two
n-stage
cells
A
and
B
in
parallel
between
source
Vs
and
output
VO.
For
each
cell,
there
includes
n
capacitors
C1,
C2
Cn,
&
3n-1switches
S1
,S2
...S3
(i.e.,
power
or
complementary
MOSFETS),
where
each
capacitor
has
capacitance
C
with
equivalent
series
resistance
(ESR)
rc
,
and
similarly
theoutput
capacitor
has
capacitance
C0
with
ESR
rc0,
and
MOSFETS
S
,S2
.S3n-I
are
operated
as
static
switches
with
the
on-state
resistance
rT
.
According
to
the
scheduledoperation
of
Fig.3,
it
is
obvious
that
both
cells
A
and
B
are
basically
operated
in
anti-phase:
when
cell
A
is
in
the
capacitor-charging
period,
cell
B
is
working
in
the
capacitor-discharging
period,
and
vice
versa.
So,
the
duty
cycle
is
fixed
at
0.5
for
each
cell.
Here,
in
the
first
half-cycleperiod,
let
QSA
be
in
pinch-offregion
as
a
controlled
current
source,
turn
off
SA
&
QSB,and
turn
on
SB
in
triode
region
as
a
small
resistor.
Then,
n
capacitors
CAI
-CAn
of
cell
A
are
linearly
charged
in
series
by
the
constant
controlled
1652
I
IcellB
Ir--
q--
_-
iCell
B
v
a
t
t
 
0.5,
such
a
constant
duty
cycle
is
much
useful
especially
to
control
design
and
theoreticalanalysis.
First,
for
the
aim
to
steady-state
analysis,
based
on
the
formulation
of
(1),
around
one
static
operating
point,
all
voltages
and
currents
are
divided
into
two
parts:static
+
operating
points
and
dynamic
small
signals
as:
IRL
vO
VCa
(t)
=
Vca
+
VCa
(t)
VCb
(t)
=
VCb
+
VCb
(t),
(2a,b)
Vco
(t)
=
VCO
+
VCo
(t),
D
(t)
=
'D
+
ld
(t)
,
vO
(t)
=
VO
+
io
(t)
,
VGS
(t)
=
VGS
+
1gs
(t)
I
(2c,d)
(2e,f)
I
&
SB
c,
t'
,l
S
ti
SHIt
IC1
2
-]
S
-I]
ag
Co
I
11
Fig.4
n-stage
QSC
step-down
DC-DC
converter
current
source,
and
at
the
same
time,
n
capacitors
CBR1
CBn
of
cell
B
are
discharged
in
parallel
to
supply
the
load
RL
.
Based
on
the
same
idea,
in
the
second
half-
cycle,
they
exchange
their
works.
By
this
way,
charging
in
series
and
discharging
in
parallel
for
n
capacitors
cyclically,
the
step-down
function
can
be
realized
to
keep
output
on
Vs/n
ideally.
Here,
for
simplification,since
all
capacitors
of
cells
A
and
B
are
selectedidentically
by
the
value
of
C,
i.e.
CA=
=CAn=
CB1=
=CB=
C,
the
voltage
drop
across
each
capacitor
of
the
same
cell
is
assumed
identical,
denoted
by
vca
(t)
and
VCb
(t)
for
capacitor
voltage
incells
A
and
B,
respectively.
According
to
these
two
circuit
topologies
(charging
into
n
capacitors
in
series
and
discharging
from
n
capacitors
in
parallel),
a
completely
state-space
averaged
description
of
n-stage
QSC
step-down
DC-DC
converter
of
Fig.4
can
be
derived
as
rc(
+RL
vCa'(t)-
2nC
A
VC'(t)
=
0
-vco'(t)j
RL
2C.
A
[VO(t)]=
rco
RL
LA
O
RL
2nC
A
rcO
+
RLRL
2nC-A
2nC
A
RL
rl
+
rT
+
RL
2C,
.
A
Co-A
vCa(t)
2C
V.
VC(t)
+
0
rCORL
(rl+rT)-RL
V
(t)
VCb
(t)
L-Vco@
(0
where
r1
=
((C
+
2rT)/n,
(1
c)
A
=
(rT
+rl)(rc,
+RL)+rC,RL,
(Id)
iD
(t)
is
the
average
drain
current
of
QSA/QSB,
and
vo
(t),
Vco
(t)
represent
the
load
voltage
and
output
capacitorvoltage,
respectively.
In
this
research,
such
a
QSC
configuration
is
adopted
with
increasing
some
advantages
as
follows.(1)
Since
theinterleaved
current-mode
technique
is
adopted,
the
inputcurrent
Is
can
be
constant
continuously.
The
input
current
waveform
hasno
high
current
peak/jump,
so
that
EMI
problem
is
improved
greatly.(2)
Since
all
the
elements
in
power-part
circuit
contain
only
MOSFETS
and
capacitors,
the
uniform
feature
is
helpful
to
I.C.
fabrication
and
realization.
(3)
Since
the
two
cellsare
working
complementarily,
i.e.,
the
duty
cycle
is
fixed
at
where
VCa,Vcb,
VCo,
ID,Y
VGS
represent
the
static
signals,
and
CaC,
vCb,
C,d
Id,
io
3gs
are
the
dynamic
small
signals.
By
substituting
states
variation
x'(t)
=0
of
(1),
thesteady-stateoutput
VO
and
J0
can
be
shown
as
*Steady-state
analysis
and
expression:
VO=-CavAav
Ba
u=
nRLID
=
n
-LK(VGS
-Vt)2,
(3a)
k0
=VO/RL
=n
ID
=n-K(VGs
Vt)2,
(3b)
where
K
is
the
process
parameter
of
MOSFET,
and
Vt
is
the
threshold
voltage.
Here,
it
is
notable
that
both
output
voltage
VO
and
output
current
J0
are
not
function
of
source
Vs
.
In
other
words,
when
the
source
Vs
is
decreasing
a
little,
such
a
source
variation
cannot
affect
output
VO
&
J0
immediately.
Since
Vs
is
not
directly
connected
to
the
load
RL
at
any
half-cycle
of
period,
the
variation
of
source
Vs
will
not
make
any
immediate
response
on
output
VO
and
Jo.
That
is
a
very
excellent
advantage
for
QSC
converter,so
it
could
have
better
output
robustnessagainst
source
variation
or
noise.
Based
on
the
conclusion
of
(3),
thesteady-state
input/output
power
of
QSC
converter
can
be
computed
as:
Pi
VS
IS=
VS
ID,
(4a)
Po
VO
10
RL
I0
=
VO
*nIID
(4b)
Thus,
using
Equations
(4a)-(4b),the
power
conversion
efficiency
of
converter
is
derived
as
Equation
(5),
where
M
=
VO
/Vs
represents
the
voltage
conversion
ratio.
P
V=
n
-ID
=n.
VO
=n.M.
(5)
Pi
VS
ID
VS
[iD(6)],
Next,
around
some
static
operating
point,
followed
by
using
the
small-signal
analysis,the
dynamic
equation
can
be
presented
in
Equation
(6),
and
consequently
the
small-
signal
transfer
function
of
the
QSC
step-down
converter
can
be
also
suggested
in
Equation
(7):
(la,b)
*Small-signal
state-space
expression:
Svc
I(t)
_-
L
o(t)j-L
rco
+RL
2nC
A
RL
CO
-A
RL
2nC
A
~(t)
gm~
+
2C
[,o
rT
+
rl+RL
L~co(t)i
0
Co
-A
FrCO
RL
(ri
+
rT
)RL
AA
LCo
(t)j
*Small-signal
transfer
function
expression:
(6a,b)
gmrCoRL(+1)
G
(s)
V
0
(s)
2C-A
rCCO(7)
gS
)
(
)2+
Co
(rco
+RL)+2nC(rT
+rl
+RL)
1S+
I
2nCCO
A
2nCCO
A
where
airgm
ig
,and
g
=2K
ID/K
is
the
trans-
conductance.
If
the
QSC
step-down
converter
is
regarded
as
an
open-loop
plant
of
control
system,
then
its
small-
signal
open-loop
model
has
been
derivedhere
withtwo
forms
of:
state-space
and
transfer
function
expression
as
1653

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