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Kautz Mesh Topology for on-Chip Networks

R. Sabbaghi-Nadooshan

Abstract— During the recent years, 2D mesh Network-on-Chip has attracted much attention due to its suitability for VLSI
implementation. This paper introduces the 2-dimensional Kautz topology for Network-on-Chips as an attractive alternative to the
popular simple 2D mesh. The cost of 2D Kautz is equal to that of the simple 2D mesh but it has a logarithmic diameter. We
compare the proposed network and the mesh network in terms of power consumption and network performance. Compared to
the equal sized simple mesh NoC, the proposed Kautz-based network has better performance while consuming less energy.
Also by vertically stacking two or more silicon wafers, connected with a high-density and high-speed interconnect, it is now
possible to combine multiple active device layers within a single IC. In this paper we propose an efficient three dimensional
layout for a novel 2D mesh structure based on the Kautz topology. Simulation results show that by using the third dimension,
performance and latency can be improved compared to the 2D VLSI implementation.

Index Terms— 3D layout, 3D NoCs, Kautz, NoCs, Performance evaluation, Power consumption, SoC.

——————————  ——————————

1 INTRODUCTION

N owadays there are many challenges in designing a

complicated integrated circuit containing several
processing and memory elements integrated on a
single chip as a System-on-Chip (SoC). SoC design has
some limitations in the DSM technologies. One of the ma-
jor problems associated with future SoC designs arises
from non-scalable global wire delays [1]. These limita-
tions have been mentioned in many studies [1][2] includ-
ing the limitation in the number of IP cores that can be
connected to the shared bus, arbitration for accessing the
shared bus, reliability, and so on. To overcome these limi-
tations, network-on-chip (NoC) is introduced in recent
years and much research has been conducted in this area.
A proper classification of these studies has been discussed
in [3]. Another new technology that has been proposed is
the three dimensional VLSI that exploits the vertical di-
mension to alleviate interconnect related problems and to
facilitate heterogeneous integration of technologies to
realize a SoC design [4]. By combining the ideas in these
two types of technology, a new kind of architecture for
NoCs is imaginable. In [5], new insights on network to-
pology design for 3D NoCs is provided and issues related
to processor placement across 3D layers and data man-
agement in L2 caches is addressed. In three dimensional
designs with the aid of small links between adjacent lay-
ers, there is a noticeable improvement in network per-
formance.
The performance and also the power consumption of
the circuit mainly depend to the traffic pattern, routing
algorithm, switching method, and topology. Some com-
mon structures have been used for NoC implementations
including mesh and torus networks.
The mesh topology is the most dominant topology for
today’s regular tile-based NoCs. It is well known that
————————————————
• R. Sabbaghi-Nadooshan is with the Department of Electronics, Islamic
Azad University Central Tehran Branch, Tehran, Iran.
mesh topology is very simple. It has low cost and con-
sumes low power. During the past years, much effort has
been made toward understanding the relationship be-
tween power consumption and performance for mesh
based topologies [6]. Despite the advantages of meshes
for on-chip communication, some packets may suffer
from long latencies due to lack of short paths between
remotely located nodes. A number of previous works try
to tackle this shortcoming by adding some application-
specific links between distant nodes in the mesh [7] and
bypassing some intermediate nodes by inserting express
channels [8], or using some other topologies with lower
diameter [9].
The fact that the Kautz network has a logarithmic di-
ameter and a cost equal to the linear array topology moti-
vated us to evaluate it as an underlying topology for on-
chip networks. Kautz topology is a well-known network
structure which was initially proposed by Kautz [10] as
an efficient topology for parallel processing. Several re-
searchers have studied topological properties, routing
algorithms, efficient VLSI layout and other important
aspects of the de Kautz networks [11].
In this paper, we propose a two-dimensional Kautz-
based mesh topology for NoCs. We will compare equiva-
lent mesh and 2D Kautz architectures using the two most
important performance factors, network latency and
power consumption. A routing scheme for 2D Kautz
network has been developed and the performance and
power consumption of the two networks under similar
working conditions has been evaluated using simulation
experiments. Simulation results show that the proposed
network can outperform its equivalent popular mesh to-
pology in terms of network performance and energy dis-
sipation.
Furthermore, we propose an efficient 3D VLSI layout
for the 2D Kautz topology and we show that still it is
possible to improve performance by using 3D VLSI tech-
nologies.
The rest of the paper is organized as follows. The next
section presents the 2D Kautz structure. Section 3 dis-
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cusses the background in NoC, 3D VLSI, and explains the while it imposes almost the same cost.
characteristics of 3D designs that may affect the perfor-
mance of 3D NoCs. Also the 3D VLSI layout of the 2D
Kautz structure is discussed in section 3. Section 4 ex-
plains the simulation environment that the results have
obtained in it, and then the simulation results and expe-
rimental evaluation of our approach are described. Final-
ly, we conclude the paper in section 5.

2 K AUTZ TOPOLOGY
2.1 Kautz architecture
A class of digraphs that generalize Kautz digraphs [10] is
defined in [11]. Suppose that the vertices are numbered
with integers modulo N (N being the number of nodes).
Assuming an out-degree of d, then a vertex v is joined to
vertices u = -dv - i (mod N), for i=1, 2, …, d. The diameter
of the resulting digraph is at most log d N and if N=dn+dn-k
(for a positive odd integer k), the diameter becomes n.
Based on the above definition, an N-node binary Kautz
digraph is then defined as follows. Node v, with a linear
address 0…N-1, is joined to vertices with integer address -
2v-1 (mod N) and -2v-2 (mod N).
An 8-node binary Kautz digraph is depicted in Fig. 1.
Each node generates two connections to other nodes and Fig. 2. 8×8 2D Kautz
accepts two connections from other nodes. Owing to the
fact that these connections are unidirectional, the degree 2-3 Layout improvement
of the network is the same as the one-dimensional mesh
Based on the necklace properties in de Bruijn layout [13],
networks. The diameter of a Kautz network with size N is
we have considered a more efficient layout for each row
log (N) which is the minimum distance between nodes 0
and column of the Kautz as shown in Fig. 3. With this
and N.
new layout the total wire length used in the network is
decreased. For example, for an 8×8 2D Kautz about 57%
reduction in total wire length is obtained.

5 4 1 7 0 3 6 2
Fig. 1. 1D Kautz network with 8 nodes.

2-2 Two dimensional Kautz Fig. 3. A better node placement of Kautz network
The 2D Kautz networks have some interesting topological
properties which motivates us to consider them as a suit-
able candidate for on-chip network architectures [12]. The 2-4 Routing algorithm
architecture of this network is depicted in Fig. 2. In this
Kautz graph has similarities to de Bruijn graph [11], and
network, the nodes in each row and column form a Kautz
for routing algorithm we adopt the routing methods in-
network. The most important property is that while the
troduced in [14] by Park as a common routing scheme
number of links in a 2D Kautz and an equal-size mesh are
when developing routing algorithms for the 2D Kautz
exactly the same, the network diameter of the 2D Kautz is
networks.
less than the diameter of the mesh.
Park’s algorithm uses virtual channels unevenly where
The Kautz links are unidirectional and the maximum
very few packets use all the virtual channels. Numbering
of 8 unidirectional links per node in the Kautz equals to
virtual channels in an increasing order starting from 0, it
the maximum number of links for mesh nodes (which are
uses virtual channel 0 more than other virtual channels.
4 bidirectional links). Since the node degree of a topology
For example, for N=16, some of the source nodes use only
has an important contribution in (and usually acts as the
virtual channel 0, some nodes use virtual channels 0 and
dominant factor of) the network cost, the proposed topol-
1, and a few source nodes use virtual channels 0, 1, and 2.
ogy can achieve lower average distance than a 2D mesh
This routing algorithm was revised to make a more ba-
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lanced use of virtual channels. Here, at each node, the
packet has a degree of flexibility in selecting virtual chan-
nels [9]. For the same example of N=16 given above, the
last group of source nodes (that use 3 virtual channels),
virtual channel 0 is selected to inject the message. For the
second group, packets start their journey with virtual
channel 1, and for the first group (using 1 virtual channel)
they start with virtual channel 2. If a message wants to
start with virtual channel 2 and it is occupied, it can try
virtual channel 1, and if it is also occupied it can try start-
ing with virtual channel 0. Through this method, the vir-
tual channels are used more uniformly that results in a
more balanced traffic over network channels. Fig. 4 shows
the pseudo code of the routing algorithm.
In this paper, we apply the routing algorithm given in
Fig. 4. To this end, a message first routes the packet in X
dimension using the above-mentioned routing algorithm
in such a way that the route length be minimal. When the
x-value of the current node and x-value of the destination
node addresses become equal, the packet is then routed to
the destination by applying the same routing algorithm in
the destination columns. Note that routing in the two di-
mensions cannot generate cyclic dependencies as the base
routing algorithm in each dimension is deadlock-free and
the packets travel the network in a dimension order.
Therefore, the resulted routing algorithm is deadlock-
free.
Algorithm Routing (C, D, Vadd, VC)
Inputs: Current node C=(XC, YC); Destination node
D=(Xd, Yd);
Current sub-graph indicator Vadd;
Current virtual channel VC;
Begin
If (C=D) then return EjectionChannel;
If (XC#Xd) then
(PC, g) = Next-Node-X (XC, Xd);
If Vadd= decreasing and g=increasing then VC++;
Vadd=g;
return (PC, VC);
Endif;
If (YC#Yd) then
(PC, g) = Next-Node-Y (YC, Yd);
If Vadd= decreasing and g=increasing then VC++;
Vadd=g;
return (PC, VC);
Endif;
Fig. 4. The pseudo code of the routing algorithm
. three dimensional designs [4, 16, 17, 18]. Most of such
3. 3D VLSI TECHNOLOGIES
There are four basic components in every NoC that
should be considered: 1) Processing elements that are the
IP cores connected by the network; 2) Routers and
switches that route the packets till received at destination;
3) Network adapters that are the interface between PEs
and switches; 4) Links that connect two adjacent switches.
When analyzing the network, the behavior of these com-
ponents should be considered carefully. A different set of
constraints exists when adapting these architectures to
the SoC design paradigm. High throughput and low la-
tency are the desirable characteristics of a multiprocessor
system. Instead of aiming strictly for speed, designers
increasingly need to consider energy consumption con-
straints, especially in the SoC domain [15]. So, in order to
compare different NoC architectures, there are some im-
portant metrics that should be considered such as net-
work latency, energy consumption, and throughput [15].
In this paper, these metrics are investigated in mesh and
2D Kautz architectures in the context of 3D VLSI.
Presently, there are several possible fabrication tech-
nologies that can be used to realize multiple layers of ac-
tive-area (single crystal Si or re-crystallized poly-Si) sepa-
rated by interlayer dielectrics (ILDs) for 3D circuit
processing). A brief description of these alternatives is
given in [4].
Generally, there are some main advantages using the
third dimension in VLSI design and these advantages can
be very useful in NoC architectures. The benefits of 3D
ICs include: 1) higher packing density due to the addition
of a third dimension to the conventional two-dimensional
layout, 2) higher performance due to reduced average
interconnect length, and 3) lower interconnect power con-
sumption due to the reduction in total wiring length [5].
Furthermore, the 3D chip design technology can be ex-
ploited to build SoCs by placing circuits with different
voltage and performance requirements in different layers
[4]. The first benefit is true for conventional circuits and
also for NoC architectures. For example, if 64 IP cores in a
NoC architecture are organized in a 3D network instead
of 2D organization, the chip area reduces almost four
times and we will have more integration in design. In
conventional integrated circuits, the length of global
wires is very important in latency and power consump-
tion especially in emerging deep sub-micron technologies.
In NoC architectures, even though wires are invariable in
size, links between vertical layers can be very short in
comparison with the links in each layer in the second di-
mension. The shorter the links are, the less power they
consume. The last benefit is very amazing in SoC design
that is applicable in NoC architectures. The digital and
analog components in the mixed-signal systems can be
placed on different Si layers, thereby achieving better
noise-performance due to lower electromagnetic interfe-
rence between such circuit blocks [4].
Many studies have investigated the performance of
evaluations are based on wire-length distributions. It
means that a stochastic 3D interconnect model is pre-
sented and the impact of 3D integration on circuit per-
formance and power consumption is investigated. In this
study, our attention is focused on a network architecture
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point of view of three dimensional technologies.
There are some characteristics and constraints that
should be considered when designing 3D architectures.
The characteristics of conventional VLSI are still impotant
in the second dimension even in a 3D design context.
A) Latency in vertical communications: Vertical links, due
to their small length, provide fast communication be-
tween vertical layers. For instance, in a 70nm technology,
the distance between adjacent vertical layers is about 3-70
micron. If a 4x inverter drive the link, it takes about 7ps
that is not considerable in comparison with the links in
horizontal communications [15]. So, the capacitance and
resistance of these links are different. In [17, 18], the link
between two components in different active layers is split
into two parts: horizontal and vertical that are different in
resistance and capacitance.
B) Vertical link density in 3D technologies: The density of
links in vertical communications is limited by fabrication
process. It means that the space between vertical channels
is limited. Via pitch in different processes is variable be-
tween 1 to 7 micron [15, 19]. The constraints on links may
result in limitation in bus bandwidth. Compared to a wire
pitch of 0.1 µm, inter-layer vias are significantly larger
and cannot achieve the same wiring density as intra layer
interconnects [5].
C) Area overhead of vertical links: As mentioned, there is
limitation in density of vertical links, so they may take
significant area in each layer. It may be about 10 percent
of the area occupied by routers and switches [5].
D) Complexity of NoC routers: One inter-layer intercon-
nects option is to extend the NoC into three dimensions.
This requires the addition of two more links (up and
down) to each router. However, adding two extra links to
a NoC router will increase its complexity (from 5 links to
7 links) [5].
E) Heat dissipation: An extremely important issue in 3D
ICs is heat dissipation. The problem is expected to be ex-
acerbated by the reduction in chip size, assuming that
same power generated in a 2D chip will now be generat-
ed in a smaller 3D chip, resulting in a sharp increase in
the power density [4]. So, the number of active layers in
3D technologies is usually limited to 4 or 5 layers.
F) Different layers: Different layers may be processed by
different technologies, so the characteristics of each layer
may differ and should be considered in simulation.
3.1. THE 3D VLSI LAYOUT OF 2D KAUTZ
In our proposed layout, we assume 4 layers for the 3D
implementation of the network and 64 nodes are distri-
buted in these 4 layers. Fig. 3 (in the previous section) can
be changed to Fig. 5 for 4 layers spanning in three dimen-
sions.
In Fig. 5, each node represents a row of the network
shown in Fig. 2. For instance, Row#5 has 8 nodes that
each of these nodes is connected with a unidirectional
link to its counterpart in Row#4, and Row#7 has 8 nodes
that each of them is connected with a bidirectional link to
its counterpart in Row#0.
By connecting vertical nodes with fast vertical intecon-
nects, the performance of 3D structure outperforms the
2D implementations. The area of the chip is also reduced
by nearly two times. Moreover, this structure has another
useful characteristic: There are fewer links between nodes
in layer#0 and so the power that dissipates in this layer is
less than the upper layers. This feature can be beneficial
in 3D architectures because of the heat dissipation in 3D
VLSI technologies.
Fig.5. 3D VLSI layout of 2D Kautz architecture.
4. SIMULATION ENVIRONMENT
To simulate the proposed NoC topologies, an intercon-
nection network simulator that is developed based on
POPNET [20] with an embedded latest version of Orion
power library [21] was used. Providing detailed power
characteristics of the network elements, Orion enables the
designers to make rapid power evaluation at the architec-
ture level [21].
The POPNET simulator was modified to mimic the ex-
act operation of the 2D mesh and the 2D Kautz NoCs. The
simulator was also customized to support other topolo-
gies and other routing algorithms such as shuffle-
exchange [22], de Bruijn[23],and Kautz topologies [12].
The power consumption can be obtained for each compo-
nent of the network and for each layer (if implemented
using 3D VLSI technology).
For each simulated network, the physical link width
was assumed to be 32 bits. The power was calculated
based on a NoC with 90 nm technology whose routers
operate at 250 MHz. Based on the core size information
presented in [24], the side size of each IP core was set to 2
mm, and the length of each wire was set based on the
number of cores it passes through.
The message length was assumed to be M=32 flits and
V=2 virtual channels per physical channel were used. At
each node, messages were generated according to a Pois-

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son distribution with an average generation rate of λ mes-
sages per cycle. The simulations were performed under
uniform, matrix-transpose, and hotspot [25] traffic pat-
terns.
Note that for matrix-transpose traffic load, it was as-
sumed that 30% of the messages generated by a node
were of matrix-transpose type (i.e. node (x,y) sends a
message to node (y,x)) and the rest of the messages were
sent to other nodes uniformly. In hotspot traffic load, a
hotspot rate of 16% was assumed, i.e. each node sent 16%
of messages to the hotspot node (which is assumed to be
node (4,0) in the 88 network) and the rest of messages
were sent to other network nodes uniformly.
4.1. SIMULATION RESULTS
In Fig. 6(a), the average message latency is displayed as a
function of message generation for the 8×8 2D mesh and
2D Kautz NoCs using V=2 virtual channels per physical
channel and for two different message sizes M=32 flits
under various traffic patterns.
As can be seen in the Fig. 6(a), the 2D Kautz NoC
achieves a reduction in message latency with respect to
the simple 2D mesh network for the full range of network
load under various traffic patterns. Non-fixed lengths will
also result in some variations in the delay and power of
the network links. Since the operating frequency of a NoC
is often determined by the longest router pipeline stage,
the long wires may not degrade the NoC operating fre-
quency. This can be achieved by segmenting long links
into regular fixed length links connected by 1-flit buffers.
The size of each segment equals to the size of a link con-
necting two adjacent nodes. Using 1-flit buffers (which is
inspired from pipelined circuit switching methods in
conventional interconnection networks [25]) provides
pipelining over the link and also acts as a repeater for it.
By sending the flits of a message over a long link in a pi-
pelined fashion, latency-insensitive operation is guaran-
teed as discussed in [7]. Note that we have taken this pi-
pelined transmission into account in the simulation, as
(a)
Fig. 6. Average delay and total power comparison between two-dimensional Kautz and mesh structure.
well as the effect of buffers and link lengths in the power
consumption.
Fig. 6(b) depicts power consumption of the considered
networks under various traffics. As shown in the figure,
the 2D Kautz can effectively reduce the power consump-
tion of the NoC compared to the equivalent mesh topolo-
gy. The main source of such a noticeable reduction is the
less hop counts taken by the messages (on average) and
hence saving the power which is consumed in interme-
diate routers in an equivalent mesh topology.
In Fig. 7, the average latency and power consumption
in 3D and 2D implementation of Kautz structure is
shown. In this section, the latency of horizontal links in
each layer are nearly 10 times slower than vertical links.
In the case of uniform traffic, the 3D structure has lower
latency because of fast vertical links in the network.
Smaller links consumes less power and so it can affect the
total power consumption.
One of the main characteristics of 3D technologies is
reduction in power dissipation of links in the network.
Fig. 8(a) compares total power that dissipates in links in
the case of 2D and 3D structures. The results show that
with the aid of vertical links the power dissipation de-
creases nearly 40 %. The 3D layout that has been pro-
posed in this paper has an important characteristic in
three-dimensional designs. The lower layers in the archi-
tecture consume less power because of fewer links and so
less traffic in the layers. This feature can reduce the effect
of heat dissipation in 3D VLSI designs. Fig. 8(b) shows
thepower that dissipates in each four layers of the struc-
ture.
(b)
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(a) (b)

Fig. 7. Average delay and total power comparison between three and two dimensional implementation of Kautz structure (Vertical links
are 10 times faster than horizontal links).

(a) (b)
Fig. 8. a) Total link power comparison between three and two dimensional implementation of Kautz. b) Layer Power consumption.

Fig. 9. The area overhead of 8x8 and 16x16 digraph-based mesh NoCs with different buffer depths
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4.2 Area overhead
The area overhead due to the additional inter-router
wires was analyzed by calculating the number of chan-
nels in a NoC. An n×n 2-d mesh has 2n(n-1) channels. The
2D Kautz NoCs have the same number of channels al-
though some links use longer wires. To evaluate the im-
posed area overhead, we estimated the area of the routers
and links using Orion 2.0 tool [26]. The area of the router
was calculated in 90nm technology.
In the analysis, the lengths of input and output net-
work interface buffers were considered as large as 64 flits.
This was a modest size for the network interface queues.
In Table 3, the area overhead of a Kautz NoC is eva-
luated for 88 networks. The results show that in an 88
mesh the total area of the links and routers are 0.0366
mm2 and 0.2742 mm2, respectively. Based on these area
estimations, the area of the network part of the 2-D Kautz
network shows a 22% increase compared to the 2-D mesh
NoC of equal size. Considering 2mm×2mm processing
elements, the increase in the entire chip area is about 2%.
It is noteworthy that the router area is a function of its
buffers depth. The depth of the input and output buffers
of the routers, in this paper, were set to 2 flits (or 4-flit
buffer at each port). A performance analysis in [27], how-
ever, showed that a typical router in next generation
high-performance CMPs (using 22nm technology) will
need 64-flit buffers at each port, which result in a higher
router/switch area. Fig. 9 plots the area overhead of the
2D Kautz NoCs over a mesh with (the same size and buf-
fering capacity) for network size N=88 and different
buffer depths in a system with 32-bit channels. Based on
Fig. 9, a system using 64-flit buffers reduces the area
overhead of the 2D Kautz networks to about 9%.
Table 1
Area Comparison
Added
Link Router Added area with
Network Area Area area (Per- respect to
(mm2) (mm2) centage) the whole
chip
64-node
0.0366 0.2742 0 0
2D Mesh
64-node
0.0627 0.2742 22.75 2.08
2DKautz
5 CONCLUSION
The simple 2D mesh topology has been widely used in
a variety of interconnection network applications espe-
cially for NoC design. However, the Kautz network
has not been studied yet as the underlying topology
for 2D tiled NoCs. In this paper, we introduced the
two-dimensional Kautz network which has the same
cost as the popular mesh, but has a logarithmic diame-
ter. We then conducted a comparative simulation
study to assess the network latency and power con-
sumption of the two networks. Results showed that the
2D Kautz topology improves the network latency es-
pecially for heavy traffic loads. The power consump-
tion in the 2D Kautz network was also less than that of
the equivalent simple 2D mesh NoC. Furthermore, in
this paper, a 3D VLSI layout for the 2D Kautz is pro-
posed and this design has caused to further decrease
thepower consumpsion, especially in the NoC links.
Combination of Kautz with other topologies can be
a challenging future work in this line.
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R. Sabbaghi-Nadooshan received the B.S. and M.S. degree in

electrical engineering from the Science and Technology University,