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Abstract—This paper presents two new 1-bit full adder topologies operating in subthresold region in 65nm technology. Circuits designed
in this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computational
building blocks. A modification was done to optimize W/L ratios with different supply voltages using the conventional 1.5:1 for Wp/Wn.
Compared with a previously reported minority-3 based full adder; the results involve better performance in terms of power, delay, and
PDP.
—————————— ——————————
1 INTRODUCTION
entiation of I ds , n with respect to Vgs is proportional and NOR functions, we set the substrate voltage at
Vdd/2, 0 and Vdd respectively. These blocks have been
to I ds , n . Thus, the conductivity of the transistor, across the designed and simulated by HSpice using the 65nm stan-
drain and source terminals could be controlled by the dard CMOS technology at supply voltage of 0.2V and
substrate and gate terminal voltages. with switching frequency of 6.66 MHZ. We used W/L
ratios for all the PMOS transistors 1.5 times the ratio of
3-DESIGN OF INVERSE MAJORITY, NAND W/L for all NMOS transistors. The output signals de-
rived from the simulations are brought in Fig. 3.
AND NOR GATES IN SUB THRESHOLD RE-
GION 4-MINORITY-3 BASED 1-BIT FULL ADDER
Fig. 1 shows a block of 6 transistors, all are working in Minority-3 based 1-bit full adder is depicted in figure 4(a).
sub threshold region. In order to keep the transistors in Majority not gates are replaced with block of 6 transistors.
sub this region, it is required that Vdd be less than |Vth| This full adder has been simulated with the same condi-
of both NMOS and PMOS. In other words, considering
tions. A load capacitor of 60fF (is equaled with 10*C gs )
the worse case ,that is the input signal has the value of
Vdd, Vgs xNMOS= V= Vdd .Note that Vgs xNMOS is the was put at the output. Output wave forms derived from
x Hspice simulation are depicted Fig. 4 (b).
voltage across gate and source of the transistor with its
gate connected to input x. To keep it in sub threshold re-
gion it is required, Vgs xNMOS < Vth . Since
Vgs xNMOS= V=
x Vdd , this leads to Vdd < Vth . According
to equation 1, an increase in substrate voltage causes an
increase in I ds of NMOS transistors as well as a decrease
in I ds of PMOS transistors. As mentioned earlier, the con-
ductivity of a transistor is related to I ds , thus the resis-
Fig. 1. Block of 6 transistors used to implement inverse majori-
tance of transistor has an inverse relation with I ds . ty, NAND, NOR gates in sub threshold region[4].
Table 1
Functionality of the first proposed 1-bit Full Adder
(a)
(b)
Fig. 5. (a) The first proposed 1-bit Full Adder. (b) A com-
plete scheme.
(b)
the power versus Vdd that introduces minority-3 based 1- Simulations were done at three supply voltages, ranging
bit full adder, consumes maximum power and the second from 0.25v down to 0.18v. Results have shown that our
proposed design consumes minimum power for range circuits had the least power consumption and PDP in
Vdds, 0.18, 0.2 and 0.25. Fig. 12(b) shows the delay versus most cases in comparison with minority-3 based 1-bit full
Vdd that indicates in value 0.18 for Vdd, the first pro- adder.
posed design has minimum delay and in value 0.25 for
Vdd, the second proposed design has least delay. Fig.
12(c) shows the PDP versus Vdd that illustrates in values
0.18, 0.2, and 0.25 for Vdd, the second proposed has least
delay. Best values for power, delay and PDP from minori-
ty-3 based 1-bit full adder, the first and second design
simulations are reported in Table 2.
=
Cout majority ( A, B, Cin) (8)
(a)
(b)
Fig. 7. (a) The second proposed 1-bit full adder. (b) A com-
plete scheme.
7-SUMMARY AND CONCLUSION Fig. 9. (a) Average power measurements from minority-3
Two novel low-power 1-bit full adder cells have been based 1-bit full adder. (b) Worst case delay, (c) PDP
proposed. The first design uses majority-not, NAND and
NOR gates which are implemented using 6 transistor in
subthreshold region. The second design uses two majori-
ty-not gates, which the first majority-not gate has three
inputs and the second majority-not gate has five inputs in
subthreshold region. The second design has fewer transis-
tors than the first one. Low power consumption has been
targeted at the circuit design level for both cells.
JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151-9617
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Fig. 12. (a) Power versus supply voltage. (b) Delay versus
supply voltage. (c) PDP versus supply voltage.
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Table 2.
Best values for power, delay and PDP
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