JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151-9617

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Two Subthreshold Full Adder Cells in 65 nm CMOS Tech-

nology

M. Alizadeh, B. Forouzandeh, and R. Sabbaghi-Nadooshan

Abstract—This paper presents two new 1-bit full adder topologies operating in subthresold region in 65nm technology. Circuits designed
in this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computational
building blocks. A modification was done to optimize W/L ratios with different supply voltages using the conventional 1.5:1 for Wp/Wn.
Compared with a previously reported minority-3 based full adder; the results involve better performance in terms of power, delay, and
PDP.

Index Terms—full adder, inverse majority gate, Subthreshold, VLSI.

——————————  ——————————

1 INTRODUCTION

T here are a number of applications in which low pow-

er consumption is given a high priority among other
design concerns. Applications such as wrist watches,
based 1-bit full adder mentioned in [4]. Majority not gates
are replaced with block of 6 transistors (Min3 IJCNN).
The output wave forms are showed in this section. In sec-
hearing aids, and portable communication systems are tion 5, the proposed full adder structures as well as out
among them. Sub-threshold operation provides compel- put wave forms from Hspice simulations are drawn.
ling solution for a number of emerging energy- Study of their characteristics is explained in section 6.
constrained systems [1]. In this paper we proposed two Section 7 is dedicated to summary and conclusion
new structures for 1- bit full adder cell based on the sub
threshold perceptron introduced in [2],[3]. These struc- 2-DISCUSSION OF TRANSISTORS IN SUB
tures have been simulated and their results are compared THRESHOLD REGION
with simulation results of minority-3 based 1-bit full ad- For an NMOS transistor operating in sub threshold re-
der [4], [5]( Min3 IJCNN Based on the dynamically recon- gion, the current between drain and source is expressed
figurable “IJCNN”-element [2],[6] that configured as a as in equation (1) [8].
minority-3 gate by biasing the wells of the element). The
input waveforms contain all the possible transitions from  κ Vgs   Vbs    −Vds  Vds  (1)
one input combination to another (56 patterns) [7], [8].
I ds ,n =
I 0 exp   exp (1 − κ ) 1 − exp  + 
 t 
V  V t    Vt  V0 
The accuracy and characteristics of the structures have
been investigated and reported in the following sections. Here, I 0 is a constant and shows the current between
The paper is organized as follows. drain and source while the transistor is in zero bias and it
is affected by the length and width value of the transistor.
In section 2, behavior of transistors in sub threshold re-
gion is described in brief. The idea of using substrate ter- V0 is the Early voltage and is proportional to L. κ is a
minal voltage to control resistance of transistors in sub coefficient with which the channel current is related to the
threshold region is introduced in this section. Using this gate voltage and is approximately variable between 0.7 to
intuition, a block of 6 transistors (IJCNN [4]) proposed in 0.75 V. Vt is the thermal voltage and is equal to kT . Equ-
[4], [5], [9] has been used to design three input gates of q
inverse majority, NAND and NOR and the output wave ation 1 shows that the substrate and the gate voltages
forms derived from Hspice simulations are brought in
have the capability to control I ds , n . In other words,
Section 3. In section 4, it is considered the minority-3
———————————————— ∂ I ds I ds
g= = (2)
• M. Alizadeh is with the Scientific Association of Electrical& Electronic m ds
∂Vds V0
Engineering, Islamic Azad University Central Tehran Branch, Te-
hran,Iran. ∂ I ds κ I ds
• B. forouzandeh is with the Department of Electrical and Computer =
gm = (3)
E,university of Tehran,Tehran,Iran ∂ Vgs Vt
• R. Sabbaghi-Nadooshan is with the Department of Electronics, Islamic
Azad University Central Tehran Branch, Tehran,Iran.
As shown in the equations (2) and (3) [9], the conductiv-
ity between drain and source (g m ds ) as well as the differ-
R R
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entiation of I ds , n with respect to Vgs is proportional and NOR functions, we set the substrate voltage at
Vdd/2, 0 and Vdd respectively. These blocks have been
to I ds , n . Thus, the conductivity of the transistor, across the designed and simulated by HSpice using the 65nm stan-
drain and source terminals could be controlled by the dard CMOS technology at supply voltage of 0.2V and
substrate and gate terminal voltages. with switching frequency of 6.66 MHZ. We used W/L
ratios for all the PMOS transistors 1.5 times the ratio of
3-DESIGN OF INVERSE MAJORITY, NAND W/L for all NMOS transistors. The output signals de-
rived from the simulations are brought in Fig. 3.
AND NOR GATES IN SUB THRESHOLD RE-
GION 4-MINORITY-3 BASED 1-BIT FULL ADDER
Fig. 1 shows a block of 6 transistors, all are working in Minority-3 based 1-bit full adder is depicted in figure 4(a).
sub threshold region. In order to keep the transistors in Majority not gates are replaced with block of 6 transistors.
sub this region, it is required that Vdd be less than |Vth| This full adder has been simulated with the same condi-
of both NMOS and PMOS. In other words, considering
tions. A load capacitor of 60fF (is equaled with 10*C gs )
the worse case ,that is the input signal has the value of
Vdd, Vgs xNMOS= V= Vdd .Note that Vgs xNMOS is the was put at the output. Output wave forms derived from
x Hspice simulation are depicted Fig. 4 (b).
voltage across gate and source of the transistor with its
gate connected to input x. To keep it in sub threshold re-
gion it is required, Vgs xNMOS < Vth . Since
Vgs xNMOS= V=
x Vdd , this leads to Vdd < Vth . According
to equation 1, an increase in substrate voltage causes an
increase in I ds of NMOS transistors as well as a decrease
in I ds of PMOS transistors. As mentioned earlier, the con-
ductivity of a transistor is related to I ds , thus the resis-
Fig. 1. Block of 6 transistors used to implement inverse majori-
tance of transistor has an inverse relation with I ds . ty, NAND, NOR gates in sub threshold region[4].

Vth= Vth 0 + γ ( | 2Φ F + VSB | − | 2Φ F |) (4)

Here, γ denotes the body effect coefficient, and VSB is the

source-bulk potential difference. Φ F is given by
kT N where N sub is the doping concentration of the
ln( sub )
q ni
Fig. 2. Block of figure 1, the inputs x and y are zero and the
substrate. Equation (4) [10] shows the relation between
input z is vdd.
the threshold voltage and substrate terminal voltage. In-
creasing the threshold voltage of a PMOS by an increase
in substrate terminal voltage causes an increase in the
resistance of PMOS. In another point of view, as the tran-
sistor goes toward being off, it shows more resistance. In
Fig. 2(a) [2], [9] regarding to V gs and V bs values are de-
termined resistor values and in figure 2(b) [5], resistors
with greater value are depicted bigger in size. Transistors
making the nonlinear resistive network determine the
output voltage [9]. Resistors with greater value represent
the transistors which are further deep toward being off.
Resistors with smaller sizes represent transistors with
smaller |V th |, which are about to become on, still being
in sub threshold region because of power considers. As
shown in Fig. 2, each transistor is considered as a four
terminal device, resistance of which is controlled by its Fig. 3. The inputs a, b and cin and the outputs inverse majority,
gate and substrate terminal voltages. The complex of 6 NAND and NOR. (Vdd=0.2, f=6.66 MHZ)
such resistors, producing a voltage divider, determines
the output voltage as depicted in Fig. 2. A complete de-
scription of this block is found in [9]. In order to imple-
ment the three input gates of inverse majority, NAND
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5-DESIGN OF TWO 1-BIT FULL ADDERS IN
SUB THRESHOLD
5-1Proposed Design 1
The functionality of the first proposed 1-bit Full Adder
with A, B and Cin (input carry) inputs, and Sum and Cout
(output carry) outputs, can be described by equation (5)
and table 1. The primary design of the first proposed 1-bit
full adder is depicted in Fig. 5(a). Substituting the de-
signed inverse majority, NAND and NOR blocks from
section 3, we reach to the new sub threshold full adder. A
load capacitor of 20fF (is equaled with 10*C gs ) was put at
the output. It has been simulated with the same condi-
tions as mentioned in section 3. The complete scheme and
output wave forms are depicted in Fig. 5(b) and figure 6,
respectively.
Cout = majority (A,B,Cin)
Table 1
Functionality of the first proposed 1-bit Full Adder
(a)
(b)
Fig. 4. (a) Minority-3 based 1-bit full adder (Min3
IJCNN) [4], [5]. (b) Output wave forms. (Vdd=0.2, f=6.66
MHZ)
170
5-2 Proposed Design 2
The functionality of the second proposed 1-bit Full Adder
with A, B and Cin (input carry) inputs, and Sum and Cout
(output carry) outputs, can be described by equation (6)
and (7) [11]. The second proposed primary design of 1-bit
full adder is depicted in Fig. 7(a). The first block is a three
input inverse majority gate and the second block is a five
input one. It should be noticed that the inverse majority
of inputs, a, b, and Cin is cout . sum is the majority of five
inputs, a, b, Cin and two cout s. The three input inverse
majority gate could be implemented by the block of figure
1, as done in the first design. While the five input one
could simply be implemented by adding two more paral-
leled inverters to the block of Fig. 1, making it a ten tran-
sistor structure.
(5)
(b)
Fig. 5. (a) The first proposed 1-bit Full Adder. (b) A com-
plete scheme.
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The complete scheme of the second 1-bit Full adder is
depicted in Fig. 7(b). A load capacitor of 1fF (is equaled
with 10*C gs ) was put at the output. This structure has
also been simulated with the same conditions as in design
1, however w/L ratios in design 2 is chosen by far less than
design 1 due to power considerations. Output wave
forms are depicted Fig. 8.
Fig. 6. Output wave forms from the full adder of Fig. 5.
(Vdd=0.2, f=6.66 MHZ)
6-SIMULATION RESULTS
The two new structures and minority-3 based 1-bit full
adder, have been designed and simulated by Hspice in
65nm standard CMOS technology at three different val-
ues for supply voltage. The results have been compared
with each others. We simulated all full adder cells at
various frequencies ranging from 33.3 Hz to 33.3 MHz.
Values of 0.25V, 0.2V, and 0.18V were chosen for Vdd and
at each value of supply voltage, characteristics of the two
new structures plus minority-3 based 1-bit full adder,
were investigated for a range of different W / L s for
NMOS transistors. We used the same W / L ratios for all
NMOS transistors, as mentioned previously. Values
of W / L for PMOS transistors were always kept 1.5 times
those of the NMOS transistors. The average power con-
sumption of the simulated circuits is calculated by the
following equation [12], [13]:
171
(6)
P dynamic denotes the switching component of power
where, Vdd is the power supply voltage; ƒ clk is the sys-
tem clock frequency, and V swing is the voltage swing of
the output, C iload is the output load capacitance at node
i, and α i is the transmission activity factor at node i.
P short − circuit represent the short-circuit power, which re-
sults from I isc following from power supply to ground at
node i. P static denotes the leakage power, which is derived
from leakage current I l which is due to reverse-biased
junction leakage current and subthreshold leakage cur-
rent. The delay of cells has been measured from the mo-
ment that the inputs reach 50% of the supply voltage level
to the moment that the latest of the Sum and Cout signals
reach the same voltage level. All transitions from one in-
put to another (56 patterns) have been checked and the
delay has been measured for each transition. The maxi-
mum has been reported as the delay of each cell. Finally,
for general comparison, the power-delay product (PDP)
was calculated by following equation [11]:
PDP = Maximum Delay* Average Power (7)
The results are reported in nine different diagrams shown
in Fig. 9, Fig. 10 and Fig. 11. The first three diagrams
represent the power, propagation delay and PDP of mi-
nority-3 based 1-bit full adder that has been simulated
with Hspice. The second three diagrams represent the
power, propagation delay and PDP of first design derived
from simulations. Fig. 11 shows three diagrams of power,
delay and PDP from simulation of design 2. Each diagram
has three different sets of numbers attributed to three
different values of Vdd. Diagrams in Fig. 9(a, b) show that
increasing W/L or Vdd causes the power consumption to
increase in minority-3 based 1-bit full adder, while it
causes the delay to decrease. Fig. 9(c) shows that increas-
ing the W/L causes the PDP to increase. Also, increasing
Vdd causes a decrease in PDP. Fig. 10 (a, b) shows that
increasing W/L or Vdd causes the power consumption to
increase and the delay to decrease in the first proposed
design. Fig. 10(c) shows that increasing W/L causes a de-
crease and then an increase in PDP. Also, increasing Vdd
causes an increase in PDP. Fig. 11(a, b) show that increas-
ing W/L or Vdd causes increase in power consumption
and delay in the second proposed design. Fig. 11(c) shows
that increasing W/L causes the PDP to increase and in-
creasing Vdd causes the PDP to decrease. The diagrams
of power versus Vdd, delay versus Vdd and PDP versus
Vdd are shown in Fig. 12 for minority-3 based 1-bit full
adder, proposed design 1 and design 2. Fig. 12(a) shows
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the power versus Vdd that introduces minority-3 based 1- Simulations were done at three supply voltages, ranging
bit full adder, consumes maximum power and the second from 0.25v down to 0.18v. Results have shown that our
proposed design consumes minimum power for range circuits had the least power consumption and PDP in
Vdds, 0.18, 0.2 and 0.25. Fig. 12(b) shows the delay versus most cases in comparison with minority-3 based 1-bit full
Vdd that indicates in value 0.18 for Vdd, the first pro- adder.
posed design has minimum delay and in value 0.25 for
Vdd, the second proposed design has least delay. Fig.
12(c) shows the PDP versus Vdd that illustrates in values
0.18, 0.2, and 0.25 for Vdd, the second proposed has least
delay. Best values for power, delay and PDP from minori-
ty-3 based 1-bit full adder, the first and second design
simulations are reported in Table 2.

=
Cout majority ( A, B, Cin) (8)

sum = Majority ( A, B, Cin, Cout , Cout ) (9)

=
sum Majority not ( A, B, Cin, Cout , Cout )

(a)

(b)

Fig. 7. (a) The second proposed 1-bit full adder. (b) A com-
plete scheme.

Fig. 8. Output wave forms for the full adder of figure 7.

(Vdd=0.2, f=6.66 MHZ)

7-SUMMARY AND CONCLUSION Fig. 9. (a) Average power measurements from minority-3
Two novel low-power 1-bit full adder cells have been based 1-bit full adder. (b) Worst case delay, (c) PDP
proposed. The first design uses majority-not, NAND and
NOR gates which are implemented using 6 transistor in
subthreshold region. The second design uses two majori-
ty-not gates, which the first majority-not gate has three
inputs and the second majority-not gate has five inputs in
subthreshold region. The second design has fewer transis-
tors than the first one. Low power consumption has been
targeted at the circuit design level for both cells.
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Fig. 11. (a) Average power measurements from proposed

design 2. (b) Worst case delay, (c) PDP

Fig. 10. (a) Average power measurements from proposed

design 1. (b) Worst case delay, (c) PDP

Fig. 12. (a) Power versus supply voltage. (b) Delay versus
supply voltage. (c) PDP versus supply voltage.
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Table 2.
Best values for power, delay and PDP

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