JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151-9617HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG 168
Two Subthreshold Full Adder Cells in 65 nm CMOS Tech-nology
M. Alizadeh, B. Forouzandeh, and R. Sabbaghi-Nadooshan
This paper presents two new 1-bit full adder topologies operating in subthresold region in 65nm technology. Circuits designedin this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computationalbuilding blocks. A modification was done to optimize W/L
ratios with different supply voltages using the conventional 1.5:1 for Wp/Wn.Compared with a previously reported minority-3 based full adder; the results involve better performance in terms of power, delay, andPDP.
full adder, inverse majority gate, Subthreshold, VLSI.
here are a number of applications in which low pow-er consumption is given a high priority among otherdesign concerns. Applications such as wrist watches,hearing aids, and portable communication systems areamong them. Sub-threshold operation provides compel-ling solution for a number of emerging energy-constrained systems . In this paper we proposed twonew structures for 1- bit full adder cell based on the subthreshold perceptron introduced in ,. These struc-tures have been simulated and their results are comparedwith simulation results of minority-3 based 1-bit full ad-der , (
Min3 IJCNN Based on the dynamically recon-figurable “IJCNN”-element , that configured as aminority-3 gate by biasing the wells of the element). Theinput waveforms contain all the possible transitions fromone input combination to another (56 patterns) , .The accuracy and characteristics of the structures havebeen investigated and reported in the following sections.The paper is organized as follows.In section 2, behavior of transistors in sub threshold re-gion is described in brief. The idea of using substrate ter-minal voltage to control resistance of transistors in subthreshold region is introduced in this section. Using thisintuition, a block of 6 transistors (IJCNN ) proposed in, ,  has been used to design three input gates ofinverse majority, NAND and NOR and the output waveforms derived from Hspice simulations are brought inSection 3. In section 4, it is considered the minority-3based 1-bit full adder mentioned in . Majority not gatesare replaced with block of 6 transistors (Min3 IJCNN).The output wave forms are showed in this section. In sec-tion 5, the proposed full adder structures as well as output wave forms from Hspice simulations are drawn.Study of their characteristics is explained in section 6.Section 7 is dedicated to summary and conclusion
For an NMOS transistor operating in sub threshold re-gion, the current between drain and source is expressedas in equation (1) .
exp exp (1 ) 1 exp
gsbs ds dsds nt t t
V V V V I I V V V V
−= − − +
is a constant and shows the current betweendrain and source while the transistor is in zero bias and itis affected by the length and width value of the transistor.
is the Early voltage and is proportional to L.
is acoefficient with which the channel current is related to thegate voltage and is approximately variable between 0.7 to0.75 V.
is the thermal voltage and is equal to
. Equ-ation 1 shows that the substrate and the gate voltageshave the capability to control
. In other words,
ds dsm dsds
I I gV V
ds dsmgs t
I I gV V
As shown in the equations (2) and (3) , the conductiv-ity between drain and source (g
) as well as the differ-
M. Alizadeh is with the Scientific Association of Electrical& ElectronicEngineering, Islamic Azad University Central Tehran Branch, Te-hran,Iran.
B. forouzandeh is with the Department of Electrical and Computer E,university of Tehran,Tehran,Iran
R. Sabbaghi-Nadooshan is with the Department of Electronics, IslamicAzad University Central Tehran Branch, Tehran,Iran.