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Two Subthreshold Full Adder Cells in 65 nm CMOS Technology

Two Subthreshold Full Adder Cells in 65 nm CMOS Technology

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Journal of Computing, ISSN 2151-9617, http://www.journalofcomputing.org
Journal of Computing, ISSN 2151-9617, http://www.journalofcomputing.org

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Published by: Journal of Computing on Mar 10, 2011
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JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151-9617HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG 168
Two Subthreshold Full Adder Cells in 65 nm CMOS Tech-nology
M. Alizadeh, B. Forouzandeh, and R. Sabbaghi-Nadooshan
 
Abstract
This paper presents two new 1-bit full adder topologies operating in subthresold region in 65nm technology. Circuits designedin this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computationalbuilding blocks. A modification was done to optimize W/L
 
ratios with different supply voltages using the conventional 1.5:1 for Wp/Wn.Compared with a previously reported minority-3 based full adder; the results involve better performance in terms of power, delay, andPDP.
Index Terms
full adder, inverse majority gate, Subthreshold, VLSI.
 

 
 

1 I
NTRODUCTION
here are a number of applications in which low pow-er consumption is given a high priority among otherdesign concerns. Applications such as wrist watches,hearing aids, and portable communication systems areamong them. Sub-threshold operation provides compel-ling solution for a number of emerging energy-constrained systems [1]. In this paper we proposed twonew structures for 1- bit full adder cell based on the subthreshold perceptron introduced in [2],[3]. These struc-tures have been simulated and their results are comparedwith simulation results of minority-3 based 1-bit full ad-der [4], [5](
 
Min3 IJCNN Based on the dynamically recon-figurable “IJCNN”-element [2],[6] that configured as aminority-3 gate by biasing the wells of the element). Theinput waveforms contain all the possible transitions fromone input combination to another (56 patterns) [7], [8].The accuracy and characteristics of the structures havebeen investigated and reported in the following sections.The paper is organized as follows.In section 2, behavior of transistors in sub threshold re-gion is described in brief. The idea of using substrate ter-minal voltage to control resistance of transistors in subthreshold region is introduced in this section. Using thisintuition, a block of 6 transistors (IJCNN [4]) proposed in[4], [5], [9] has been used to design three input gates ofinverse majority, NAND and NOR and the output waveforms derived from Hspice simulations are brought inSection 3. In section 4, it is considered the minority-3based 1-bit full adder mentioned in [4]. Majority not gatesare replaced with block of 6 transistors (Min3 IJCNN).The output wave forms are showed in this section. In sec-tion 5, the proposed full adder structures as well as output wave forms from Hspice simulations are drawn.Study of their characteristics is explained in section 6.Section 7 is dedicated to summary and conclusion
2-DISCUSSION
 
OF
 
TRANSISTORS
 
IN
 
SUB
 
THRESHOLD
 
REGION
For an NMOS transistor operating in sub threshold re-gion, the current between drain and source is expressedas in equation (1) [8].
, 00
exp exp (1 ) 1 exp
gsbs ds dsds nt t
V V I V V V
κ κ 
 = +
(1)
Here,
0
is a constant and shows the current betweendrain and source while the transistor is in zero bias and itis affected by the length and width value of the transistor.
0
is the Early voltage and is proportional to L.
κ 
is acoefficient with which the channel current is related to thegate voltage and is approximately variable between 0.7 to0.75 V.
is the thermal voltage and is equal to
kT q
. Equ-ation 1 shows that the substrate and the gate voltageshave the capability to control
,
ds n
. In other words,
0
ds dsm dsds
I gV
 
= =
(2)
ds dsmgs
I gV
κ 
= =
(3)
As shown in the equations (2) and (3) [9], the conductiv-ity between drain and source (g
R
m ds
R
) as well as the differ-

 
 
M. Alizadeh is with the Scientific Association of Electrical& ElectronicEngineering, Islamic Azad University Central Tehran Branch, Te-hran,Iran.
 
B. forouzandeh is with the Department of Electrical and Computer E,university of Tehran,Tehran,Iran
 
 
R. Sabbaghi-Nadooshan is with the Department of Electronics, IslamicAzad University Central Tehran Branch, Tehran,Iran.
T
 
JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151-9617HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG 169
entiation of
,
ds n
with respect to
gs
is proportionalto
,
ds n
. Thus, the conductivity of the transistor, across thedrain and source terminals could be controlled by thesubstrate and gate terminal voltages.
3-DESIGN
 
OF
 
INVERSE
 
MAJORITY,
 
NAND
 
AND
 
NOR
 
GATES
 
IN
 
SUB
 
THRESHOLD
 
RE-GION
Fig. 1 shows a block of 6 transistors, all are working insub threshold region. In order to keep the transistors insub this region, it is required that Vdd be less than |Vth|of both NMOS and PMOS. In other words, consideringthe worse case ,that is the input signal has the value ofVdd,
gs xNMOS x d
V V
 
= =
.Note that
gs xNMOS
 
is thevoltage across gate and source of the transistor with itsgate connected to input x. To keep it in sub threshold re-gion it is required,
gs xNMOS th
V
 
<
. Since
gs xNMOS x d
V V
 
= =
, this leads to
dd th
V
<
. Accordingto equation 1, an increase in substrate voltage causes anincrease in
ds
of NMOS transistors as well as a decreasein
ds
of PMOS transistors. As mentioned earlier, the con-ductivity of a transistor is related to
ds
, thus the resis-tance of transistor has an inverse relation with
ds
.
0
( | 2 | | 2 |)
th th F SB
V V
γ  
= + Φ + − Φ
(4)Here,
γ  
denotes the body effect coefficient, and
SB
is thesource-bulk potential difference.
Φ
is given by
ln( )
subi
kT q n
where
sub
is the doping concentration of thesubstrate. Equation (4) [10] shows the relation betweenthe threshold voltage and substrate terminal voltage. In-creasing the threshold voltage of a PMOS by an increasein substrate terminal voltage causes an increase in theresistance of PMOS. In another point of view, as the tran-sistor goes toward being off, it shows more resistance. InFig. 2(a) [2],
 
[9] regarding to
gs
and
bs
values are de-termined resistor values and in figure 2(b) [5], resistorswith greater value are depicted bigger in size. Transistorsmaking the nonlinear resistive network determine theoutput voltage [9]. Resistors with greater value representthe transistors which are further deep toward being off.Resistors with smaller sizes represent transistors withsmaller |V
th
4-MINORITY-3
 
BASED
 
1-BIT
 
FULL
 
ADDER
|, which are about to become on, still beingin sub threshold region because of power considers. Asshown in Fig. 2, each transistor is considered as a fourterminal device, resistance of which is controlled by itsgate and substrate terminal voltages. The complex of 6such resistors, producing a voltage divider, determinesthe output voltage as depicted in Fig. 2. A complete de-scription of this block is found in [9]. In order to imple-ment the three input gates of inverse majority, NANDand NOR functions, we set the substrate voltage atVdd/2, 0 and Vdd respectively. These blocks have beendesigned and simulated by HSpice using the 65nm stan-dard CMOS technology at supply voltage of 0.2V andwith switching frequency of 6.66 MHZ. We used W/Lratios for all the PMOS transistors 1.5 times the ratio ofW/L for all NMOS transistors. The output signals de-rived from the simulations are brought in Fig. 3.Minority-3 based 1-bit full adder is depicted in figure 4(a).Majority not gates are replaced with block of 6 transistors.This full adder has been simulated with the same condi-tions. A load capacitor of 60fF (is equaled with 10*C
gs
)was put at the output. Output wave forms derived fromHspice simulation are depicted Fig. 4 (b).
Fig. 1. Block of 6 transistors used to implement inverse majori-ty, NAND, NOR gates in sub threshold region[4].Fig. 2. Block of figure 1, the inputs x and y are zero and theinput z is vdd.Fig. 3. The inputs a, b and cin and the outputs inverse majority,NAND and NOR. (Vdd=0.2, f=6.66 MHZ)
 
 
JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151-9617HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG 170
5-DESIGN
 
OF
 
TWO
 
1-BIT
 
FULL
 
ADDERS
 
IN
 
SUB
 
THRESHOLD
5-1Proposed Design 1
The functionality of the first proposed 1-bit Full Adderwith A, B and Cin (input carry) inputs, and Sum and Cout(output carry) outputs, can be described by equation (5)and table 1. The primary design of the first proposed 1-bitfull adder is depicted in Fig. 5(a). Substituting the de-signed inverse majority, NAND and NOR blocks fromsection 3, we reach to the new sub threshold full adder. Aload capacitor of 20fF (is equaled with 10*C
gs
) was put atthe output. It has been simulated with the same condi-tions as mentioned in section 3. The complete scheme andoutput wave forms are depicted in Fig. 5(b) and figure 6,respectively.
Cout = majority (A,B,Cin) (5)
Table 1Functionality of the first proposed 1-bit Full Adder
(a)(b)
Fig. 4. (a) Minority-3 based 1-bit full adder (Min3IJCNN) [4], [5]. (b) Output wave forms. (Vdd=0.2, f=6.66MHZ)
 
5-2 Proposed Design 2
The functionality of the second proposed 1-bit Full Adderwith A, B and Cin (input carry) inputs, and Sum and Cout(output carry) outputs, can be described by equation (6)and (7) [11]. The second proposed primary design of 1-bitfull adder is depicted in Fig. 7(a). The first block is a threeinput inverse majority gate and the second block is a fiveinput one. It should be noticed that the inverse majorityof inputs, a, b, and Cin is
cout 
.
sum
is the majority of fiveinputs, a, b, Cin and two
cout 
s. The three input inversemajority gate could be implemented by the block of figure1, as done in the first design. While the five input onecould simply be implemented by adding two more paral-leled inverters to the block of Fig. 1, making it a ten tran-sistor structure.(b)
Fig. 5. (a) The first proposed 1-bit Full Adder. (b) A com-plete scheme.

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