Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Save to My Library
Look up keyword
Like this
9Activity
0 of .
Results for:
No results containing your search query
P. 1
rr420203-vlsi-design

rr420203-vlsi-design

Ratings: (0)|Views: 226 |Likes:
Published by SRINIVASA RAO GANTA

More info:

Published by: SRINIVASA RAO GANTA on Aug 26, 2008
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

07/29/2014

pdf

text

original

Code No: RR420203
Set No. 1
IV B.Tech II Semester Supplimentary Examinations, May 2008
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1. (a) Find gm and rds for an n-channel transistor with
VGS = 1.2V;Vtn = 0.8V; W/L = 10;\u00b5nCox = 92\u00b5A/V2 and VDS = Ve\ufb00 +
0.5V
The out put impedance constant.\u03bb =95.3\u00d7 10\u22123 V\u22121
(b) Explain the term Figure of merit of a MOS Transistor.
[10+6]
2. (a) With neat sketches explain how resistors and capacitors are fabricated in p-
well process.
(b) With neat sketches explain how resistors and capacitors are fabricated in n-
well process.
[8+8]
3. Design a stick diagram for the PMOS logic shown below
[16]
Y=(A +B).C
4. Design a layout diagram for the CMOS logic shown below
[16]
Y=(A +B +C )
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 104\u2126 per square.
[16]
Figure 5
1 of 2
Code No: RR420203
Set No. 1
6. With neat sketch explain clearly the architecture of the PROM.
[16]
7. With respect to synthesis process explain the following terms.

(a) Flattening
(b) Factoring.
(c) Mapping.

[6+5+5]
8. Mention di\ufb00erent growth technologies of the thin oxides and explain about any one
technique.
[16]
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
2 of 2
Code No: RR420203
Set No. 2
IV B.Tech II Semester Supplimentary Examinations, May 2008
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1. (a) Explain with neat sketches the Drain and Transfer characteristics of n-channel
enhancement MOSFET.
(b) With neat sketches explain the transfer characteristics of a CMOS inverter.
[10+6]
2. (a) Compare between CMOS and bipolar technologies.
(b) With neat sketches explain nMOS fabrication process.
[8+8]
3. Design a stick diagram for the NMOS logic shown below
[16]
Y= (A+ B+ C)
4. Design a layout diagram for nMOS inverter.
[16]
5. Calculate the gate capacitance value of 5\u00b5m technology minimum sized transistor
with gate to channel capacitance value is 4\u00d7 10\u22124pF /\u00b5m2.
[16]
6. (a) What are the advantages and disadvantages of the recon\ufb01guration.
(b) Mention di\ufb00erent advantages of Anti fuse Technology.
[8+8]
7. (a) What is the goal of VHDL synthesis step in design \ufb02ow?
(b) Explain how register transfer level description provides optimized synthesis
netlist.
[8+8]
8. Clearly explain the wire bonding technology of the die bonding.
[16]
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1 of 1

Activity (9)

You've already reviewed this. Edit your review.
1 thousand reads
1 hundred reads
sososoro liked this
ocimarf liked this
Muhammad Ashiq liked this
Mahender Naik liked this
hemabalan2001 liked this
Aisha Verma liked this
ragavendra4 liked this

You're Reading a Free Preview

Download
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->