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Programmable Array Logic:

PAL architecture has a programmable AND array at the input and a fixed OR array at the output.
The number of programmable AND gates is usually smaller than the number required to generate all possible
minterms of the given number of input variables. The OR array is fixed and the AND outputs are equally divided
between available OR gates.
D C B A

Hard-wired OR-array

Programmable AND-array

Y1 Y2
Fig.: Internal architecture of a PAL device.
Figure shows the internal architecture of a PAL device that has four input lines, an array of eight AND gates at the
input and two OR gates at the output.
A programmable AND gate array at the input is fed with various input variables and their complements. It allows any
of the input variables or their complements to appear at the inputs of any of the AND gates in the array. Each of the
AND gates generates a minterm of a user-defined combination of input variables and their complements.
Outputs from the programmable AND array feed an array of hard-wired OR gates. Each OR gate is fed from a subset
of AND gates in the array. This implies that the sum-of-product Boolean functions generated by each of the OR gates
at the output will have only a restricted number of minterms depending upon the number of AND gates from which it
is being fed.
Outputs from the PAL device are available both as OR outputs as well as complemented outputs.

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Example:
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1
1 0 0 1 1 0 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
Table shows the function of a converter. Starting with the Boolean expression for the four outputs (P, Q, R, S),
minimize them using Karnaugh maps and then hardware-implement this converter with a suitable PLD with PAL
architecture.
Solution:
From the given function table, the Boolean expressions for the four outputs can be written as follows.
P = A.B.C.D + A.B.C.D + A.B.C.D + A.B .C .D + A.B .C .D
Q = A.B.C .D + A.B.C .D
R = A .B .C.D + A .B .C.D + A.B.C .D + A .B.C .D + A.B.C.D + A .B.C.D
S = A .B .C .D + A .B .C.D + A .B.C.D + A.B .C .D
AB AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 x 1 00 0 1 x 0 00 0 1 x 0 00 0 0 x 1
01 0 1 x 1 01 0 1 x 0 01 0 1 x 0 01 1 0 x 0
11 0 1 x x 11 0 0 x x 11 1 1 x x 11 0 1 x x
10 0 1 x x 10 0 0 x x 10 1 1 x x 10 1 0 x x

Fig.: Karnaugh maps.

Karnaugh maps for the four outputs P, Q, R and S are shown in the figure. The minimized Boolean expressions are
given by the equations –
P = B.D + B.C + A
Q = B.C
R = B+C
S = A .B .C .D + B.C.D + A.D + B .C.D

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Ref. No............................ August 01, 2010

Dated, the………………………….

A B C D

Hard-wired OR-array

Programmable AND-array

P Q R S
Fig.: Programmed PAL.
For the given function a PAL device is needed that has –
(I) four OR gates at the output – there are four output functions.
(II) 16 AND gates in the programmable AND array – each of the OR gates is to be hard wired to only a subset of
programmable AND arrays and one of the output functions has four product terms, and

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(III) eight inputs – there are four input variables. Each AND gate in the array will have eight inputs to cater for
four variables and their complements.
Figure above shows the architecture of the programmed PAL device where an unprogrammed interconnection
indicated by a cross (x) is a make connection.
As the P output has only three product terms, the fourth input to the relevant OR gate need to be applied a logic 0
input. This is achieved by feeding the inputs of the corresponding AND gate with all four variables and their
complements.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

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