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VLSI Xilinx Manual

VLSI Xilinx Manual

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Published by aishwarya_hari

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Published by: aishwarya_hari on Mar 22, 2011
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Functional Verification
Functional verification
, inelectronic design automation,is the task of verifying that thelogic designconforms to specification. In everyday terms, functional verification attempts to answerthe question "Does this proposed design do what is intended?" This is a complex task, and takesthe majority of time and effort in most large electronic system design projects.Functional verification is very difficult - it is equivalent toprogram verification,and isNP- hardor even worse - and no solution has been found that works well in all cases. However, itcan be attacked by many methods. None of them are perfect, but each can be helpful in certaincircumstances:
Logic simulationsimulates the logic before it is built.
Simulation acceleration applies special purpose hardware to the logic simulationproblem.
Emulation builds a version of system using programmable logic. This is expensive, andstill much slower than the real hardware, but orders of magnitude faster than simulation. Itcan be used, for example, to boot the operating system on a processor.
Formal verificationattempts to prove mathematically that certain requirements (alsoexpressed formally) are met, or that certain undesired behaviors (such as deadlock) cannotoccur.
Intelligent verificationuses automation to adapt the testbench to changes intheregister transfer levelcode.
HDL-specific versions of lint,and other heuristics, are used to find common problems.Simulation based verification (also called'dynamic verification') is widely used to "simulate" thedesign, since this method scales up very easily. Stimulus is provided to exercise each line in theHDL code. A test-bench is built to functionally verify the design by providing meaningfulscenarios to check that given certain input, the design performs to specification.A simulation environment is typically composed of several types of components:
(or irritator) generates input vectors. Modern generatorsgenerate random, biased, and valid stimuli. The randomness is important to achieve a highdistribution over the huge space of the available input stimuli. To this end, users of thesegenerators intentionally under-specify the requirements for the generated tests. It is therole of the generator to randomly fill this gap. This mechanism allows the generator tocreate inputs that reveal bugs not being searched for directly by the user. Generators alsobias the stimuli toward design corner cases to further stress the logic. Biasing andrandomness serve different goals and there are tradeoffs between them, hence different
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generators have a different mix of these characteristics. Since the input for the design mustbe valid (legal) and many targets (such as biasing) should be maintained, many generatorsuse theConstraint satisfaction problem(CSP) technique to solve the complex testingrequirements. The legality of the design inputs and the biasing arsenal are modeled. Themodel-based generators use this model to produce the correct stimuli for the target design.
Thedriverstranslate the stimuli produced by the generator into the actual inputs for thedesign under verification. Generators create inputs at a high level of abstraction, namely, astransactions or assembly language. The drivers convert this input into actual design inputsas defined in the specification of the design's interface.
produces the outputs of the design, based on the design’s current state
(the state of the flip-flops) and the injected inputs. The simulator has a description of thedesign net-list. This description is created by synthesizing the HDL to a low gate level net-list.
Themonitorconverts the state of the design and its outputs to a transaction abstractionlevel so it can be stored in a 'score-boards' database to be checked later on.
The checker validates that the contents of the 'score-boards' are legal. There are caseswhere the generator creates expected results, in addition to the inputs. In these cases, thechecker must validate that the actual results match the expected ones.
The arbitration manager manages all the above components together.Differentcoveragemetrics are defined to assess that the design has been adequately exercised.These include functional coverage (has every functionality of the design been exercised?),statement coverage (has each line of HDL been exercised?), and branch coverage (has eachdirection of every branch been exercised?).Functional Verification Tools
Avery Design Systems: SimCluster (for parallel logic simulation) and Insight (for formalverification)
Obsidian Software
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Test Bench
test bench
is a virtual environment used to verify the correctness or soundness of a design ormodel (e.g., a software product).The term has its roots in the testing of electronic devices, where an engineer would sit at a labbench with tools of measurement and manipulation, such asoscilloscopes,multimeters,  soldering irons, wire cutters, and so on, and manually verify the correctness of thedevice undertest. In the context of software or firmware or hardware engineering, a test bench refers to anenvironment in which the product under development is tested with the aid of a collection of testing tools. Often, though not always, the suite of testing tools is designed specifically for theproduct under test.A test bench or testing workbench has four components.1.
The entrance criteria or deliverables needed to perform work2.
The tasks or processes that will transform the input into the output3.
The processes that determine that the output meets the standards.4.
The exit criteria or deliverables produced from the workbench
First create an empty folder in desktop to keep all your files and name it as “exercise”
 The following is the path for opening ModelSim SE:Start
All Programs
ModelSim SE 6.6c

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