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Table Of Contents

1 Introduction
2.1.1 Static RAM
2.1.2 Dynamic RAM
2.1.4 Conclusions
2.2.1 Read Access Protocol
2.2.2 Precharge and Activation
2.2.3 Recharging
2.2.5 Conclusions
2.3 Other Main Memory Users
3.1 CPU Caches in the Big Picture
3.2 Cache Operation at High Level
3.3.1 Associativity
3.3.2 Measurements of Cache Effects
3.3.4 Multi-Processor Support
3.3.5 Other Details
3.4 Instruction Cache
3.5.1 Cache and Memory Bandwidth
3.5.2 Critical Word Load
3.5.3 Cache Placement
3.5.4 FSB Influence
4.1 Simplest Address Translation
4.2 Multi-Level Page Tables
4.3.1 Caveats Of Using A TLB
4.3.2 Influencing TLB Performance
4.4 Impact Of Virtualization
5.1 NUMA Hardware
5.2 OS Support for NUMA
5.3 Published Information
5.4 Remote Access Costs
6.1 Bypassing the Cache
6.2.1 Optimizing Level 1 Data Cache Access
6.2.2 Optimizing Level 1 Instruction Cache Access
6.2.3 Optimizing Level 2 and Higher Cache Access
6.2.4 Optimizing TLB Usage
6.3.1 Hardware Prefetching
6.3.2 Software Prefetching
6.3.3 Special Kind of Prefetch: Speculation
6.3.4 Helper Threads
6.3.5 Direct Cache Access
6.4.1 Concurrency Optimizations
6.4.2 Atomicity Optimizations
6.4.3 Bandwidth Considerations
6.5.1 Memory Policy
6.5.2 Specifying Policies
6.5.3 Swapping and Policies
6.5.4 VMA Policy
6.5.5 Querying Node Information
6.5.6 CPU and Node Sets
6.5.7 Explicit NUMA Optimizations
6.5.8 Utilizing All Bandwidth
7.1 Memory Operation Profiling
7.2 Simulating CPU Caches
7.3 Measuring Memory Usage
7.4 Improving Branch Prediction
7.5 Page Fault Optimization
8.1 The Problem with Atomic Operations
8.2.1 Load Lock/Store Conditional Implementation
8.2.2 Transactional Memory Operations
8.2.3 Example Code Using Transactional Memory
8.2.4 Bus Protocol for Transactional Memory
8.2.5 Other Considerations
8.3 Increasing Latency
8.4 Vector Operations
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Published by Jordan Gray

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Published by: Jordan Gray on Mar 24, 2011
Copyright:Attribution Non-commercial


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