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Table Of Contents

Executive Overview
Defining an Exascale System
2.1 Attributes
2.1.1 Functional Metrics
2.1.2 Physical Attributes
2.1.3 Balanced Designs
2.1.4 Application Performance
2.2 Classes of Exascale Systems
2.2.1 Data Center System
2.2.2 Exascale and HPC
2.2.3 Departmental Systems
2.2.4 Embedded Systems
2.2.5 Cross-class Applications
2.3 Systems Classes and Matching Attributes
2.3.1 Capacity Data Center-sized Exa Systems
2.3.2 Capability Data Center-sized Exa Systems
2.3.3 Departmental Peta Systems
2.3.4 Embedded Tera Systems
2.4 Prioritizing the Attributes
Background
3.1 Prehistory
3.2 Trends
3.3 Overall Observations
3.4 This Study
3.5 Target Timeframes and Tipping Points
3.6 Companion Studies
3.7 Prior Relevant Studies
3.7.1 1999 PITAC Report to the President
3.7.2 2000 DSB Report on DoD Supercomputing Needs
3.7.3 2001 Survey of National Security HPC Architectural Requirements
3.7.4 2001 DoD R&D Agenda For High Productivity Computing Systems
3.7.5 2002 HPC for the National Security Community
3.7.6 2003 Jason Study on Requirements for ASCI
3.7.7 2003 Roadmap for the Revitalization of High-End Computing
3.7.8 2004 Getting Up to Speed: The Future of Supercomputing
3.7.9 2005 Revitalizing Computer Architecture Research
3.7.10 2006 DSB Task Force on Defense Critical Technologies
3.7.11 2006 The Landscape of Parallel Computing Research
Computing as We Know It
4.1 Today’s Architectures and Execution Models
4.1.1 Today’s Microarchitectural Trends
4.1.1.1 Conventional Microprocessors
4.1.1.2 Graphics Processors
4.1.1.3 Multi-core Microprocessors
4.1.2 Today’s Memory Systems
4.1.3 Unconventional Architectures
4.1.4 Data Center/Supercomputing Systems
4.1.4.1 Data Center Architectures
4.1.4.2 Data Center Power
4.1.4.3 Other Data Center Challenges
4.1.5 Departmental Systems
4.1.6 Embedded Systems
4.1.7 Summary of the State of the Art
4.2 Today’s Operating Environments
4.2.1 Unix
4.2.2 Windows NT Kernel
4.2.3 Microkernels
4.2.4 Middleware
4.2.5 Summary of the State of the Art
4.3 Today’s Programming Models
4.3.1 Automatic Parallelization
4.3.2 Data Parallel Languages
4.3.3 Shared Memory
4.3.3.1 OpenMP
4.3.3.2 Threads
4.3.4 Message Passing
4.3.5 PGAS Languages
4.3.6 The HPCS Languages
4.4 Today’s Microprocessors
4.4.1 Basic Technology Parameters
4.4.2 Overall Chip Parameters
4.4.3 Summary of the State of the Art
4.5 Today’s Top 500 Supercomputers
4.5.1 Aggregate Performance
4.5.2 Efficiency
4.5.3 Performance Components
4.5.3.1 Processor Parallelism
4.5.3.2 Clock
4.5.3.3 Thread Level Concurrency
4.5.3.4 Total Concurrency
4.5.4 Main Memory Capacity
Exascale Application Characteristics
5.1 Kiviat Diagrams
5.2 Balance and the von Neumann Bottleneck
5.3 A Typical Application
5.4 Exascale Application Characteristics
5.5 Memory Intensive Applications of Today
5.5.1 Latency-Sensitive Applications
5.5.2 Locality Sensitive Applications
5.5.3 Communication Costs - Bisection Bandwidth
5.6 Exascale Applications Scaling
5.6.1 Application Categories
5.6.2 Memory Requirements
5.6.3 Increasing Non-Main Memory Storage Capacity
5.6.3.1 Scratch Storage
5.6.3.2 File Storage
5.6.3.3 Archival Storage
5.6.4 Increasing Memory Bandwidth
5.6.5 Increasing Bisection Bandwidth
5.6.6 Increasing Processor Count
5.7.2 Projections Based on Theoretical Algorithm Analysis
5.7.3 Scaling to Departmental or Embedded Systems
5.8 Applications Assessments
5.8.1 Summary Observations
5.8.2 Implications for Future Research
Technology Roadmaps
6.1 Technological Maturity
6.2 Logic Today
6.2.1 ITRS Logic Projections
6.2.1.1 Power and Energy
6.2.1.2 Area
6.2.1.3 High Performance Devices
6.2.1.4 Low Operating Voltage Devices
6.2.1.5 Limitations of Power Density and Its Effect on Operating Frequency
6.2.2 Silicon Logic Technology
6.2.2.1 Technology Scaling Challenges
6.2.2.2 Silicon on Insulator
6.2.2.3 Supply Voltage Scaling
6.2.2.4 Interaction with Key Circuits
6.2.3 Hybrid Logic
6.2.4 Superconducting Logic
6.2.4.1 Logic Power and Density Comparison
6.2.4.2 The Memory Challenge
6.2.4.3 The Latency Challenge
6.2.4.4 The Cross-Cryo Bandwidth Challenge
6.3 Main Memory Today
6.3.1 The Memory/Storage Hierarchy
6.3.2 Memory Types
6.3.2.1 SRAM Attributes
6.3.2.2 DRAM Attributes and Operation
6.3.2.3 NAND Attributes and Operation
6.3.2.4 Alternative Memory Types
6.3.3 Main Memory Reliability - Good News
6.3.3.1 Trends in FIT Rates
6.3.3.2 Immunity to SER
6.3.3.3 Possible Issue: Variable Retention Time
6.3.4 The Main Memory Scaling Challenges
6.3.4.1 The Performance Challenge
6.3.4.2 The Packaging Challenge
6.3.4.3 The Power Challenge
6.3.4.4 Major Elements of DRAM Power Consumption
6.3.5 Emerging Memory Technology
6.4.1.4 Time to Move a Petabyte
6.4.1.5 Cost
6.4.2 Holographic Memory Technology
6.4.3 Archival Storage Technology
6.5 Interconnect Technologies
6.5.1 Strawman Interconnect
6.5.1.1 Local Core-level On-chip Interconnect
6.5.1.2 Switched Long-range On-chip Interconnect
6.5.1.3 Supporting DRAM and CPU Bandwidth
6.5.1.4 Intramodule Bandwidth
6.5.1.5 Intermodule Bandwidth
6.5.1.6 Rack to Rack Bandwidth
6.5.2 Signaling on Wire
6.5.2.1 Point-to-Point Links
6.5.2.2 Switches and Routers
6.5.3 Optical Interconnects
6.5.3.1 Optical Point to Point Communications
6.5.3.2 Optical Routed Communications
6.5.4 Other Interconnect
6.5.5 Implications
6.6 Packaging and Cooling
6.6.1 Packaging
6.6.1.1 Level 1 Packaging
6.6.1.2 Level 2 Packaging
6.6.2 Cooling
6.6.2.1 Module Level Cooling
6.6.2.2 Cooling at Higher Levels
6.7 System Resiliency
6.7.1 Resiliency in Large Scale Systems
6.7.2 Device Resiliency Scaling
6.7.3 Resiliency Techniques
6.7.4 Checkpoint/Rollback
6.8 Evolution of Operating Environments
6.9 Programming Models and Languages
6.9.1 The Evolution of Languages and Models
6.9.2 Road map
7.1 Subsystem Projections
7.1.1 Measurement Units
7.1.2 FPU Power Alone
7.1.3 Core Energy
7.1.4 Main Memory from DRAM
7.1.4.1 Number of Chips
7.1.4.2 Off-chip Bandwidth
7.1.4.3 On-chip Concurrency
7.1.5 Packaging and Cooling
7.1.6 Non-Main Memory Storage
7.2.1.4 Projections
7.2.2 Light Node Strawmen
7.2.2.1 A Baseline
7.2.2.2 Scaling Assumptions
7.2.2.3 Power Models
7.2.2.4 Projections
7.3 Aggressive Silicon System Strawman
7.3.1 FPUs
7.3.2 Single Processor Core
7.3.3 On-Chip Accesses
7.3.4 Processing Node
7.3.5 Rack and System
7.3.5.1 System Interconnect Topology
7.3.5.2 Router Chips
7.3.5.3 Packaging within a rack
7.3.6 Secondary Storage
7.3.7 An Adaptively Balanced Node
7.3.8 Overall Analysis
7.3.9 Other Considerations
7.3.10 Summary and Translation to Other Exascale System Classes
7.3.10.1 Summary: Embedded
7.3.10.2 Summary: Departmental
7.3.10.3 Summary: Data Center
7.4 Exascale Resiliency
7.5 Optical Interconnection Networks for Exascale Systems
7.5.1 On-Chip Optical Interconnect
7.5.2 Off-chip Optical Interconnect
7.6.1 Summary of Requirements
7.6.2 Phase Change in Operating Environments
7.6.3 An Aggressive Strategy
7.6.4 Open Questions
7.7 Programming Model
7.8 Exascale Applications
7.8.1 WRF
7.8.2 AVUS
7.8.3 HPL
7.9 Strawman Assessments
8.1 Major Challenges
8.1.1 The Energy and Power Challenge
8.1.1.1 Functional Power
8.1.1.2 DRAM Main Memory Power
8.1.1.3 Interconnect Power
8.1.1.4 Secondary Storage Power
8.1.2 The Memory and Storage Challenge
8.1.2.1 Main Memory
8.1.2.2 Secondary Storage
8.1.3 The Concurrency and Locality Challenge
8.1.3.1 Extraordinary Concurrency as the Only Game in Town
8.1.3.2 Applications Aren’t Going in the Same Direction
8.1.4 The Resiliency Challenge
8.2 Research Thrust Areas
8.2.1 Thrust Area: Exascale Hardware Technologies and Architecture
8.2.1.1 Energy-efficient Circuits and Architecture In Silicon
8.2.1.2 Alternative Low-energy Devices and Circuits for Logic and Memory
8.2.1.3 Alternative Low-energy Systems for Memory and Storage
8.2.1.4 3D Interconnect, Packaging, and Cooling
8.2.1.5 Photonic Interconnect Research Opportunities and Goals
8.2.2 Thrust Area: Exascale Architectures and Programming Models
8.2.2.2 Locality-aware Architectures
8.2.3 Thrust Area: Exascale Algorithm and Application Development
8.2.3.1 Power and Resiliency Models in Application Models
8.2.3.2 Understanding and Adapting Old Algorithms
8.2.3.3 Inventing New Algorithms
8.2.3.4 Inventing New Applications
8.2.3.5 Making Applications Resiliency-Aware
8.2.4 Thrust Area: Resilient Exascale Systems
8.2.4.1 Energy-efficient Error Detection and Correction Architectures
8.2.4.2 Fail-in-place and Self-Healing Systems
8.2.4.3 Checkpoint Rollback and Recovery
8.2.4.4 Algorithmic-level Fault Checking and Fault Resiliency
8.2.4.5 Vertically-Integrated Resilient Systems
8.3 Multi-phase Technology Development
8.3.1 Phase 1: Systems Architecture Explorations
8.3.2 Phase 2: Technology Demonstrators
8.3.3 Phase 3: Scalability Slice Prototype
Exascale Study Group Members
A.1 Committee Members
A.2 Biographies
B.1 Meeting #1: Study Kickoff
B.2 Meeting #2: Roadmaps and Nanotechnology
B.3 Special Topics Meeting #1: Packaging
B.4 Meeting #3: Logic
B.5 Meeting #4: Memory Roadmap and Issues
B.6 Special Topics Meeting #2: Architectures and Programming
B.7 Special Topics Meeting #3: Applications, Storage, and I/O
B.8 Special Topics Meeting #4: Optical Interconnects
B.9 Meeting #5: Report Conclusions and Finalization Plans
Glossary and Abbreviations
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exascale_final_report_100208

exascale_final_report_100208

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Published by: knpraveeenkumar on Mar 25, 2011
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