Department of E&E

II Assignment – VLSI Design (ELE 312H)

Date: 16-03-11 Submit on or before: 27-03-11

1. Draw the TG implementations of

I. 1 bit full adder
II. 1 bit full subtractor
2. For the following logic functions, design the CMOS logic gate and then sketch basic layouts
for the circuits.
I.
II.
3. An OAI function of the form is built using series-parallel CMOS
structuring.
I. Design the circuit.
II. Size the devices to get equal rise and fall times with reference to an inverter having
Wp/Wn = 2.5.
III. Expand the function into AOI form, and then apply the same sizing method. Which
design (the AOI or OAI) requires the smallest total transistor area?
4. Using transmission gates, design a circuit whose output is
I.
II.
Then optimise the circuit to reduce the transistor count.
5. With respect to the VTC of inverter, draw and compare the VTCs of 2 input NAND and NOR
gates when
I. One input is switching and other one tied to VDD
II. When both inputs tied to VDD.
Justify your explanation with spice simulations.
6. In a ring oscillator, five inverters are connected back to back. What is the maximum
oscillation frequency?