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Table Of Contents

1.1 Differential Signaling Technology
1.2 LVDS – Low-Voltage Differential Signaling
1.3 CML – Current-Mode Logic
1.4 Low-Voltage Positive-Emitter-Coupled Logic
1.5 Selecting an Optimal Technology
2.1 Point-to-Point
2.2 Multipoint / Multidrop
2.3 SerDes Architectures
2.4 Mixing Signaling Technologies
2.5 Selecting an Interface Technology
3.1 Introduction
3.2 Parallel Clock SerDes
3.3 Embedded Clock (Start-Stop) Bits SerDes
3.5 FPGA-Attach SerDes
3.6 Applications
Parallel Clock SerDes
Embedded Clock (Start-Stop) Bits SerDes
8b/10b SerDes
FPGA-Attach SerDes
3.7 Comparison Overview
3.8 Summary
4.1 Terminations and Impedance Matching
4.2 Multidrop and Multipoint
4.3 AC Coupling
4.4 DC Balance
Selecting a Capacitor
4.5 Translation
4.6 Failsafe
M-LVDS Failsafe
5.1 PCB Transmission Lines
5.2 Transmission Loss
5.3 PCB Vias
5.4 Backplane Subsystem
5.5 Decoupling
6.1 Introduction
Random Jitter Characteristics
Deterministic Jitter
Duty Cycle Distortion
Inter-Symbol Interference
Periodic Jitter
6.2 Additional Jitter Sources
Effect of Input Capacitance
Systems Susceptible to Crosstalk
Bit Error Rate
6.3 Pattern Dependencies and Eye Diagrams
Eye Masks
Bathtub Curves and Eye Contours
7.1 Physical and Electrical Cable Characteristics
7.2 Signal-Conditioning Characteristics
Media Losses in Cables and PCB Traces
Pre-Emphasis and De-Emphasis Drivers
Two Types of Equalizer Circuits
Passive: Power-Saver Equalizers
Active Equalizers
Fixed Equalizers
Variable Equalizers Allow Control
Adaptive Equalizers
7.3 Using Pre- and De-Emphasis and Equalizers Together
7.4 Random Noise
7.5 Re-clocking Receivers (Re-clockers)
Lossy Media Compensated by Equalization
Pre-Emphasis Eye Diagrams
PE/EQ Combination
8.1 Input/Output Buffer Information Specifcation
8.2 Behavioral Diagram of IBIS
8.3 3-State Output Model
8.4 Creating IBIS Models
8.5 Scattering Parameters (S Parameters)
8.6 SPICE Models
9.1 Clock Distribution and Signal Conditioning
Point-to-Point Clock Distribution
Multipoint Clock Distribution
Clock Conditioners
10.2 System Clock Distribution
ATCA-Synchronization Clock Interface
MicroTCA-Synchronization Clock Interface
9.3 Complementing FPGA Performance
Extending SerDes Enables FPGAs
Load Capacitance is Critical
LVDS Translation
9.4 Broadcast Video
9.5 Extending the Reach of SerDes
Identifying Cable-Extender-Chipset Benefts
Typical Transmission Distance Gains
Extending Signal Transmission with Conditioning
9.7 Redundancy
9.9 DVI / HDMI
10.5 Index
10.6 Acronyms
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Published by raja273

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Published by: raja273 on Mar 31, 2011
Copyright:Attribution Non-commercial


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