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Table Of Contents

1.1. Introduction
1.2. Reserved Words
1.3. Tips for Writing Good Code
1.3.1. Tip 1. Use Comments to Convey Information about the Code
1.3.2. Tip 2. Indent for Clarity and Readability
1.3.3. Tip 3. Use Standard Format Convention
1.3.4. Tip 4. Include a Header Section
1.3.5. Tip 5. Use Brief Descriptive Names
1.4. HDL Text Editors
1.4.1. Standalone Text Editor
1.4.2. Fee-Based Text Editor
1.5. Editor Features
1.5.1. Syntax Color Highlighting
1.5.2. Language Templates
1.5.3. Row and Column Editor
1.5.4. Comment/Uncomment Selected Text
1.5.5. Indent/Unindent Selected Text
1.5.6. Predefined Font Convention
1.6.1. Signal Data Types
1.6.2. Signal Names
1.7. File Structure
1.7.1. Optional Header Section
1.7.2. Library Declaration
1.7.3. Entity Section
1.7.4. Architecture Section
1.8. Starter Tips
1.9. Chapter Overview
2.1. Introduction
2.2. Starter Template
2.3. Mathematical Functions
2.7. Shift Register
2.9. Binary Counter
2.10. Conversion Functions
2.11. Read File
2.12. Write File
2.13. Chapter Overview
3.1. Introduction
3.2. What Is a Field Programmable Gate Array?
3.3. I/O Interfaces
3.4. Basic Logic Building Blocks
3.5. Ability to Interconnect
3.6. Programmable Logic Device Options
3.7. FPGA Development Phases
3.8. Chapter Overview
4.1. Introduction
4.2. What Is the Design Phase?
4.3. Design Package
4.4. Evaluating the Design Package
4.4.1. Package Analysis
4.4.2. Getting Clarification
4.4.3. Organization
4.5. Predesign Decisions
4.5.1. Design Format
4.5.2. FPGA Manufacturer
4.5.3. Development Tools
4.6. Creating Design Options
4.7. Automatic Code Generators
4.8. Manual Code Generation
4.8.1. Design Package
4.9. Chapter Overview
5.1. Introduction
5.2. What Is Simulation?
5.3. Simulation Tools
5.4. Levels of Simulation
5.6. Stimulus
5.6.1. Interactive Stimulus
5.6.2. Graphical Test Bench
5.6.3. HDL Testbench
5.6.4. Manual Testbench
5.6.5. Simulation Phase Outputs
5.6.6. Automatic Testbench
5.6.7. Capture Data
5.7. Simulation Tutorial
5.8. Chapter Overview
6.1. Introduction
6.2. What Is Design Synthesis?
6.2.1. Design Check and Resource Association
6.2.2. Optimization
6.2.3. Technology Mapping
6.3. Synthesis Phase Tools
6.3.1. Vendors and Features
6.3.2. Synthesis Tool Setup
6.4. Synthesis Input
6.5. Synthesis Output Files
6.5.1. Netlists
6.5.2. Status Reports
6.5.3. Schematic Views
6.5.4. Technology Schematic View
6.6. Synthesis Tutorial
6.7. Chapter Overview
7.1. Introduction
7.2. What Is Implementation?
7.2.1. Translate
7.2.3. Place and Route
7.2.4. Generate Program File
7.3. Implementation Tools
7.4. Implementation Inputs
7.5. Implementation Outputs
7.6. Implementation Tutorial
7.7. Chapter Overview
8.1. Introduction
8.2. What Is Programming?
8.3. Tools and Hardware
8.3.1. Joint Test Advisory Group
8.3.2. In-System Programming
8.3.3. Third Party Programmers
8.4. Hardware Configuration
8.5. Programming Tutorial
8.6. Chapter Overview
A–1. Adder and Subtractor Testbench
A–2. Logic Gates Testbench
A–3. D Flip-Flop Testbench
A–4. DFF with Synchronous Enable Testbench
A–5. Latch Design Testbench
A–6. Manual Shift Register Testbench
A–7. Comparator Testbench
A–8. Binary Counter Testbench
A–9. Binary Counter with Synchronous Enable Testbench
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FPGAs 101

FPGAs 101

Ratings: (0)|Views: 750 |Likes:
Published by Usman Ul Haq

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Published by: Usman Ul Haq on Apr 10, 2011
Copyright:Attribution Non-commercial

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05/17/2013

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