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Table Of Contents

1. Introduction
Component Creation Process Overview
1.1 Component Creation Process Overview
1.2 Conventions
1.3 References
1.4 Revision History
2. Creating Projects and Components
2.1 Cypress Component Requirements
2.1.1 File Names
2.1.2 Name Considerations
2.1.3 File Name Length Limitations
2.1.4 Component Versioning
2.2 Create a Library Project
To create a library project:
2.3 Add a New Component Item (Symbol)
2.3.1 Create an Empty Symbol
2.3.2 Create a Symbol using the Wizard
3. Defining Symbol Information
3.1.1 Formal versus Local Parameters
3.1.2 Built-In Parameters
3.1.3 Expression Functions
3.1.4 User-Defined Types
3.2 Define Symbol Parameters
3.3 Add Parameter Validators
To add a parameter validator:
3.4 Add User-Defined Types
3.5 Specify Document Properties
3.5.1 Define Catalog Placement
3.6 Define Format Shape Properties
3.6.1 Common Shape Properties
3.6.2 Advanced Shape Properties
4. Adding an Implementation
4.1 Implement with a Schematic
4.1.1 Add a Schematic
4.1.2 Complete the Schematic
4.1.2.1 Design-Wide Resources (DWR) Settings
4.2 Create a Schematic Macro
4.2.1 Add a Schematic Macro Document
4.2.2 Define the Macro
4.2.3 Versioning
4.2.4 Component Update Tool
4.2.5 Macro File Naming Conventions
4.2.5.1 Macro and Symbol with Same Name
4.2.6 Document Properties
4.2.6.1 Component Catalog Placement
4.2.6.2 Summary Text
4.2.6.3 Hidden Property
4.2.7 Macro Datasheets
4.2.8 Post-Processing of the Macro
4.2.9 Example
4.3 Implement with Verilog
4.3.1 Verilog File Requirements
4.3.2 Add a Verilog File
4.3.2.1 New File
4.3.2.2 Existing File
4.3.3 Complete the Verilog file
4.3.4 UDB Array Changes
4.3.4.1 Silicon Revision Definition
4.3.4.2 Component Configuration for Different Silicon Revisions
4.3.5 UDB Elements
4.3.5.1 Clock/Enable Specification
4.3.5.2 Datapath(s)
4.3.5.3 Control Register
4.3.5.4 Status Register
4.3.5.5 Count7
4.3.6 Fixed Blocks
4.3.7 Design-Wide Resources
4.3.8 When to use Cypress Provided Primitives instead of Logic
4.3.9 Warp Features for Component Creation
4.3.9.1 Generate Statements
localparam Usage and Named Parameters
4.4 Implement with Software
5. Simulating the Hardware
5.1 ModelSim
5.2 VCS
5.2.1 Tools
5.2.2 Test Bench Definition
6. Adding API Files
6.1 API Overview
6.1.1 API generation
6.1.2 File Naming
6.1.3 API Template Expansion
6.1.3.1 Parameters
6.1.3.2 User-Defined Types
6.1.4 Conditional API Generation
6.1.5 Verilog Hierarchy Subsitution
6.1.6 Merge Region
6.1.7 API Cases
6.2 Add API Files to a Component
6.3 Complete the .c file
6.4 Complete the .h file
7. Customizing Components
7.1 Customizers from Source
7.1.1 Protecting Customizer Source
7.1.2 Development flow
7.1.3 Add Source File(s)
7.1.4 Create Sub-Directories in “Custom”
7.1.5 Add Resource Files
7.1.6 Name the Class / Customizer
7.1.7 Specify Assembly References
7.1.8 Customizer cache
7.2 Precompiled Component Customizers
7.3 Usage Guidelines
7.3.1 Use Distinct Namespaces
7.3.2 Use Distinct External Dependencies
7.3.3 Use Common Component To Share Code
7.4 Customization Examples
7.5 Interfaces
7.5.1 System Interfaces
7.5.2 Customization Interfaces
7.5.3 Clock Query in Customizers
7.5.3.1 ICyTerminalQuery_v1
7.5.3.2 ICyClockDataProvider_v1
7.5.4 Clock API support
8. Adding Tuning Support
8.1 Tuning Framework
8.2 Architecture
8.3 Tuning APIs
8.3.1 LaunchTuner API
8.3.2 Communications API (ICyTunerCommAPI_v1)
8.4 Passing Parameters
8.5 Component Tuner DLL
8.6 Communication Setup
8.7 Launching the Tuner
8.8 Firmware Traffic Cop
8.9 Component Modifications
8.9.1 Communication Data
8.10 A simple tuner
9. Adding Bootloader Support
Firmware
9.1 Firmware
9.1.1 Guarding
9.1.2 Functions
9.1.2.1 void CyBtldrCommStart(void)
9.1.2.2 void CyBtldrCommStop(void)
9.1.2.3 void CyBtldrCommReset(void)
9.1.3 Customizer Bootloader Interface
10. Finishing the Component
Add/create datasheet
10.1 Add/Create Datasheet
10.2 Add/Create Debug XML File
10.2.1 XML Format
10.2.2 Example XML File
10.3 Add/Create Compatibility XML File
10.3.1 XML Format
10.3.2 Example .cystate File
10.4 Build the project
11. Best Practices
Clocking
11.1 Clocking
11.1.1 UDB Architectural Clocking Considerations
11.1.2 Component Clocking Considerations
11.1.3 UDB to Chip Resource Clocking Considerations
11.1.4 UDB to Input/Output Clocking Considerations
11.1.5 Metastability in Flip-Flops
11.1.6 Clock Domain Boundary Crossing
11.1.7 Long Combinatorial Path Considerations
11.1.8 Synchronous Versus Asynchronous Clocks
11.1.9 Utilizing cy_psoc3_udb_clock_enable Primitive
11.1.10 Utilizing cy_psoc3_sync Component
11.1.11 Routed, Global and External Clocks
11.1.12 Negative Clock Edge Hidden Dangers
11.1.13 General Clocking Rules
11.2 Interrupts
11.2.1 Status Register
11.2.2 Internal Interrupt Generation and Mask Register
11.2.3 Retention Across Sleep Intervals
11.2.4 FIFO Status
11.2.5 Buffer Overflow
11.2.6 Buffer Underflow
11.3 DMA
11.3.1 Registers for Data Transfer
11.3.2 Registers for Status
11.3.3 Spoke width
11.3.4 FIFO Dynamic Control Description
11.3.5 Datapath Condition/Data Generation
11.3.6 UDB Local Bus Configuration Interface
11.3.7 UDB Pair Addressing
11.3.7.1 Working Register Address Space
11.3.7.2 8-Bit Working Register Access
11.3.7.3 16-bit Working Register Address Space
11.3.7.4 16-bit Working Register Address Limitation
11.3.8 DMA Bus Utilization
11.3.9 DMA Channel Burst Time
11.5.1 Hierarchical Design
11.5.2 Parameterization
11.5.3 Component Design Considerations
11.5.3.1 Resources
11.5.3.2 Power Management
11.5.3.3 Component Development
11.5.3.4 Testing Components
11.6 Verilog
11.6.1 Warp: PSoC Creator Synthesis Tool
11.6.2 Synthesizable Coding Guidelines
11.6.2.1 Blocking versus Non-Blocking Assignments
11.6.2.2 Case Statements
11.6.2.3 Parameter Handling
11.6.2.4 Latches
11.6.2.5 Reset and Set
11.6.3 Optimization
11.6.3.1 Designing for Performance
11.6.3.2 Designing for Size
11.6.4 Resource choice
11.6.4.1 Datapath
11.6.4.2 PLD Logic
A. Expression Evaluator
A.1 Evaluation Contexts
A.2 Data Types
A.2.1 Bool
A.2.2 Error
A.2.3 Float
A.2.4 Integers
A.2.5 String
A.3 Data Type Conversion
A.3.1 Bool
A.3.2 Error
A.3.3 Float
A.3.4 Int
A.6 User-Defined Data Types (Enumerations)
B. Datapath Configuration Tool
B.1 General Functionality
Use the Datapath Configuration Tool to:
B.2 Framework
B.2.1 Interface
B.2.2 Menus
B.2.2.1 File Menu
B.2.2.2 Edit Menu
B.2.2.3 View Menu
B.2.2.4 Help Menu
B.3 General tasks
B.3.1 Launching the Datapath Configuration Tool
B.3.2 Opening a Verilog File
B.3.3 Saving a File
B.4 Working with Bit Field Parameters
B.4.1 Adding Parameter to Enumerated Bit Fields
B.4.2 Adding Parameter to Mask Bit Fields
B.4.3 Bit Field Dependencies
B.5 Working with Configurations
B.5.1 Configuration naming
B.5.2 Editing Configuration
B.5.3 Copy, Paste Configuration
B.5.4 Resetting Configuration
B.6 Working with Datapath Instances
B.6.1 Creating a New Datapath Instance
B.6.2 Deleting the Datapath Instance
B.6.3 Setting Initial Register Values
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Published by: kishorekumar.sathish407 on Apr 13, 2011
Copyright:Attribution Non-commercial

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