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A Discussion on SRAM Circuit Design

A Discussion on SRAM Circuit Design

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 5, MAY 2010 763
A Discussion on SRAM Circuit Design Trend inDeeper Nanometer-Scale Technologies
Hiroyuki Yamauchi
 , Member, IEEE 
 Abstract—
Thispapercomparesareascalingcapabilitiesofmanykinds of SRAM margin-assist solutions for variability issues,which are based on various efforts by not only the cell topologychanges from 6T to 8T and 10T but also incorporation of multiplevoltage supply for cell terminal biasing and timing sequence con-trols of read and write. The various SRAM solutions are analyzedin light of an impact on the required area overhead for each designsolution given by ever-increasing random variation
V
, re-sulting in a slowdown in the SRAM scaling pace. In order to pre-dict the area scaling trends among various SRAM solutions, twodifferent
V
-increasing scenarios of being pessimistic and op-timistic are assumed, where
V
becomes
13
mV and sup-pressed to
7
mV at the 15-nm process node, respectively. Asa result, it has been shown that the 6T SRAM cell will be allowedlong reign, even in the 15-nm process node, if 
V
can be sup-pressed to
7
mV thanks to effective oxide thickness scalingfor the low-standby-power process; otherwise, 10T and 8T withread–modify–write will be needed after
V
becomes
8
and75 mV, respectively.
 Index Terms—
Deeper nanometer scale, SRAM design solution,SRAM scaling, SRAM scaling trend.
I. I
NTRODUCTION
S
RAM IS HEAVILY modulated by random variation, so its scaling often hinges upon the future deviceand circuit technology direction. Various SRAM solutions pro-posed so far are analyzed in light of an impact on area scalinggiven by the following: 1) overall device technology scaling;2) cell topologies, including the three types of cells, namely, 6T[1]–[5], 8T [6]–[10], and 10T [11]; 3) multiple cell terminal bi-asing for read-and-write (R/W) margins assists [12]–[15]; and4) read–modify–write (RMW) timing sequence control (timemultiplexing (MUX) for R/W) for the 8T cell that can addressthe half-select issue [8].An introducing high- metal gate is the best example [7] forthe device technology scaling solution that can scale the effec-tiveoxidethickness(EOT)whileeliminatingthedepletionlayerin the gate, resulting in suppression.Conventionally, it was believed that EOT scaling had reachedthe limit due to the increase of gate leakage, and could notbe easily scaled down. However, such kind of device innovationenablesonetoextendthescalinglimitofMOSFETgate-channelsize dened by channel length width .
Manuscript received August 19, 2008; revised December 05, 2008, January14, 2009, and February 13, 2009. First published June 05, 2009; current versionpublished April 23, 2010. This work was supported in part by a Grant-in-Aidfor Scientific Research from the Japan Societyfor the Promotion of Science andfrom the Computer Science Laboratory in the Fukuoka Institute of Technology.TheauthoriswithFukuokaInstituteofTechnology,Fukuoka811-0295Japan(e-mail: yamauchi@fit.ac.jp).Digital Object Identifier 10.1109/TVLSI.2009.2016205Fig. 1. Various cell options for 32 nm and beyond.
Meanwhile, the cell topology change from 6T to 8T has beenproposed to alleviate the impact of increase on R/W sta-bility issues for SRAM scaling. However, it has come to be wellknown that the proposed 8T cell cannot solve the column inter-leaving issue for the write operation [8], [16]–[18].Toaddressthisissue,incorporationofRMWtimingsequencecontrol(timeMUXforR/W)withthe8Tcellhasbeenproposed[8], which needs an extra time for write back but can alleviatethe column interleaving issue.The10TSRAMcellhasbeenproposedtoaddressthiskindof column interleaving issue without any extra access time penaltyattheexpenseof cellareaduetotheuse oftwo moretransistors,which are used to enable a cross-point access by selected row-and-column decoding [11].On theother hand, an industry’s trend for this issue looks liketherearetwotrends for 65-and 45-nmgenerations,and botharesimilarly using a 6T cell, as shown in Fig. 1.One trend is using an SRAM supply-voltageregulator like the voltage down converter (VDC) to keep thehigher than the minimum and lowerthan the maximum voltages [20]. The other is in-corporation of offset biasing schemes for the R/W design solu-tions for the 6T cell [4], [13], [15], [19] without using VDC.Based on such trends, as shown in Fig. 1, the 6T cell can beexpectedtobesurvived,eveninthe32-nmnodeandbeyond,de-pending on the following factors: 1) amount of ; 2) whetherVDC can be incorporated; and 3) whether upsizing 6T cell toreduce is still smaller than that for the 8T cell or the 10Tcell.However, if would become larger than a certain amount,the 8T cell with RMW sequence control could be better thanupsizing 6T cell in terms of the overall SRAM core area, asdiscussed in [8], [16], and [17].
1063-8210/$26.00 © 2009 IEEE
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764 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 5, MAY 2010
Fig. 1 conceptually shows the possible options of using a dif-ferent memory cell and its control scheme for the 32-nm nodeand beyond: 1) upsizing 6T cell with a smaller for eachtransistor, 2) 8T cell with RMW (time MUX) scheme [8], and3) 10T cell with cross-point access [11].It is crucial for SRAM designers to predict when such kind of crossover happens. Because an impact on SRAM margins givenby the increasing has become increasingly severe since the65-nm node, various SRAM design solutions have been pro-posed, but no paper has compared their scaling limitations anddiscussed these kinds of trends for the 32-nm node and beyond.Therefore, the purpose of this paper is to clarify for the firsttime which design solutions will be survived until when, if will be ever increased.This paper puts primary emphasis on discussions about thefollowing: 1) R/W stability design solutions and their scalinglimits in Section II;2) various impacts of incorporating new celltopologiesand timing sequenceof RMWonscalingcapabilitiesin Sections III and IV, respectively; 3) an impact on margin-assist capability given by error checking and correcting (ECC)in Section V; and 4) comparisons of area scaling trend amongthe design solutions in Section VI, followed by conclusion.II. C
ELL
S
TABILITY
I
MPROVEMENT AND
I
TS
L
IMITATION
Cellstabilitydependsontheratiosofcelltransistorstrengths,which are referred to as the ratio for write and the ratiofor read, as well as the operation voltage . Increasingmismatch caused by random variation leads to the increaseof variations of and ratios. As a result, static noise margin(SNM) and WRM become much smaller than before at the tailsof their distributions.
 A. Read Margin Assist and Its Limitation
To increase SNM, the potential of the gate electrode of thepull-down NFET (PD_R) can be made higher than that of thepass-gate NFET (PG_R) so that the ratio becomes larger, asshown in Fig. 2(a), where the ratio is defined by the transistorstrength ratio of the PD NFET (PD_R) to PG NFET (PG_R). Inordertoimplementsucharelationship,therearetwotechniques:1) suppressed word-line (SWL) level [4], [13] and 2) boostedcell VDD level [14], [23].Fig. 2(b) shows the SNM improvements when using SWL by10% of as a function of . It can be seen that SNM isincreased by about 45 mV for an SWL level of 0.9 V atV.In addition, instead of suppressing WL, boosting CVDD alsoenables such a potential relationship between WL and CVDD.However, the design solutions for read margin improvementhave the limitation of the operating voltage window, as shownin Fig. 3. In the case of using the SWL scheme, it can be seenthat the cell current becomes too low to read at the lowerboundary due to the SWL level, as shown in Fig. 3. On the otherhand, when using the boosted CVDD scheme, a higher powersupply for the array can also become too excessive to ensuredevice reliability at the higher boundary due to the boostedCVDD level, as shown in Fig. 3.
Fig. 2. (a) SNM assist basics for 6T SRAM and (b) SNM improvement bySWL as a function of 
.Fig. 3.
windows for the SWL and boosted CVDD schemes.
 B. WRM Assist and Its Limitation
To increase WRM, the potential of the gate electrode of thepull-up PFET (PU_L) can be made lower than that of the PGNFET (PG_L) so that the ratio becomes smaller, as shownin Fig. 4(a)[12], where the ratio is defined by the transistorstrengthratioofthepull-upPFET(PU_L)toPGNFET(PG_L).In order to implement such a relationship, there are two tech-niques:1)thePDofCVDD[12] and2)negativeBLoverdriving[15]. WRM improvements when using the PD of CVDD is pro-portional to the amount of CVDD PD voltage, as shown inFig. 4(b). For example, WRM is increased by 130 mV for thePD of CVDD by 10% of at V[12].To ensure the potential of the connected node of PU andPG to be lowered than the trip point of the inverter, the neg-ative BL overdriving scheme has been proposed, as shown in
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY TIRUCHIRAPALLI. Downloaded on May 23,2010 at 14:38:18 UTC from IEEE Xplore. Restrictions apply.
 
YAMAUCHI: DISCUSSION ON SRAM CIRCUIT DESIGN TREND IN NANOMETER-SCALE TECHNOLOGIES 765
Fig. 4. (a) WRM assist basics and WRM improvements by (b) the CVDD-down scheme as a function of 
and (c) the negative BL scheme.Fig. 5.
window for the CVDD-down and negative BL schemes.
Fig. 4(b)[15]. Fig. 4(c) shows the WRM improvements whenusing the negative BL scheme as a function of . It can befoundthatWRMisincreasedbyabout280mVat V.WRM can be increased by the amount of negative BL over-driving ( 280 mV at V).In the case of using the CVDD PD scheme and the negativeBL scheme, as shown in Fig. 5, it can be seen that the cell dataretention voltage becomes too low to retain the data at the lowerboundary due to the CVDD PD level, and the applied elec-tric field becomes too excessive to ensure device reliability atthe higherboundary due to the negative BL level [15].
C. Random Variation Tren
The of MOSFET random variation is proportionalto , where is the Pelgrom coefcient [21]
Fig. 6. (a) Gate leakage scaling with different dielectrics and EOTs. (b)
 
scaling trend with and without EOT scaling.
and and are the gate channel length and width, re-spectively [21], [27], [28]. Since is proportional to EOT[21], [27], [28], it can be assumed that is proportional toas well.Fig. 6(a) shows the gate leakage scaling for different EOTsand gate materials ( , SiON, HfSiON, and other high) [24]–[26]. The 2007 International Technology Roadmapfor Semiconductors [30] shows that an upper limit of thegate leakage density is about A cm for thelow-standby-power (LSTP) process. The required EOT to meetthis target depends on the gate material. It can be found thatSiON for 1.9 nm, HfSiON for 1.6 nm, and the new high fornm are needed to suppress the maximum gate leakageV to A cm (a half-order-of-mag-nitude margin for the upper limit of for the LSTP process)[27], [30].In Tables I and II, the trends of , , EOT, andof each nMOS and pMOS are shown from 65-to 15-nm process nodes.Fig. 6(b) shows the trend of EOT and from 65- to 15-nmprocess nodes based on Tables I and II. The could be sup-pressedto mV, evenwhen the15-nm processnodeof EOTcould be successfully scaled down; otherwise, it could be in-creased up to 137 mV, as shown in Table II and Fig. 6(b).
 D. Various Assumptions to Study the Impact on Limitation of  Assist Circuits Given by That Is Increasing
1) variations are assumed as follows.a) distribution is assumed as Gaussian. Mean andsigma for systematic and random variations for
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