IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 5, MAY 2010 763
A Discussion on SRAM Circuit Design Trend inDeeper Nanometer-Scale Technologies
, Member, IEEE
Thispapercomparesareascalingcapabilitiesofmanykinds of SRAM margin-assist solutions for variability issues,which are based on various efforts by not only the cell topologychanges from 6T to 8T and 10T but also incorporation of multiplevoltage supply for cell terminal biasing and timing sequence con-trols of read and write. The various SRAM solutions are analyzedin light of an impact on the required area overhead for each designsolution given by ever-increasing random variation
, re-sulting in a slowdown in the SRAM scaling pace. In order to pre-dict the area scaling trends among various SRAM solutions, twodifferent
-increasing scenarios of being pessimistic and op-timistic are assumed, where
mV and sup-pressed to
mV at the 15-nm process node, respectively. Asa result, it has been shown that the 6T SRAM cell will be allowedlong reign, even in the 15-nm process node, if
can be sup-pressed to
mV thanks to effective oxide thickness scalingfor the low-standby-power process; otherwise, 10T and 8T withread–modify–write will be needed after
and75 mV, respectively.
Deeper nanometer scale, SRAM design solution,SRAM scaling, SRAM scaling trend.
RAM IS HEAVILY modulated by random variation, so its scaling often hinges upon the future deviceand circuit technology direction. Various SRAM solutions pro-posed so far are analyzed in light of an impact on area scalinggiven by the following: 1) overall device technology scaling;2) cell topologies, including the three types of cells, namely, 6T–, 8T –, and 10T ; 3) multiple cell terminal bi-asing for read-and-write (R/W) margins assists –; and4) read–modify–write (RMW) timing sequence control (timemultiplexing (MUX) for R/W) for the 8T cell that can addressthe half-select issue .An introducing high- metal gate is the best example  forthe device technology scaling solution that can scale the effec-tiveoxidethickness(EOT)whileeliminatingthedepletionlayerin the gate, resulting in suppression.Conventionally, it was believed that EOT scaling had reachedthe limit due to the increase of gate leakage, and could notbe easily scaled down. However, such kind of device innovationenablesonetoextendthescalinglimitofMOSFETgate-channelsize deﬁned by channel length width .
Manuscript received August 19, 2008; revised December 05, 2008, January14, 2009, and February 13, 2009. First published June 05, 2009; current versionpublished April 23, 2010. This work was supported in part by a Grant-in-Aidfor Scientiﬁc Research from the Japan Societyfor the Promotion of Science andfrom the Computer Science Laboratory in the Fukuoka Institute of Technology.TheauthoriswithFukuokaInstituteofTechnology,Fukuoka811-0295Japan(e-mail: yamauchi@ﬁt.ac.jp).Digital Object Identiﬁer 10.1109/TVLSI.2009.2016205Fig. 1. Various cell options for 32 nm and beyond.
Meanwhile, the cell topology change from 6T to 8T has beenproposed to alleviate the impact of increase on R/W sta-bility issues for SRAM scaling. However, it has come to be wellknown that the proposed 8T cell cannot solve the column inter-leaving issue for the write operation , –.Toaddressthisissue,incorporationofRMWtimingsequencecontrol(timeMUXforR/W)withthe8Tcellhasbeenproposed, which needs an extra time for write back but can alleviatethe column interleaving issue.The10TSRAMcellhasbeenproposedtoaddressthiskindof column interleaving issue without any extra access time penaltyattheexpenseof cellareaduetotheuse oftwo moretransistors,which are used to enable a cross-point access by selected row-and-column decoding .On theother hand, an industry’s trend for this issue looks liketherearetwotrends for 65-and 45-nmgenerations,and botharesimilarly using a 6T cell, as shown in Fig. 1.One trend is using an SRAM supply-voltageregulator like the voltage down converter (VDC) to keep thehigher than the minimum and lowerthan the maximum voltages . The other is in-corporation of offset biasing schemes for the R/W design solu-tions for the 6T cell , , ,  without using VDC.Based on such trends, as shown in Fig. 1, the 6T cell can beexpectedtobesurvived,eveninthe32-nmnodeandbeyond,de-pending on the following factors: 1) amount of ; 2) whetherVDC can be incorporated; and 3) whether upsizing 6T cell toreduce is still smaller than that for the 8T cell or the 10Tcell.However, if would become larger than a certain amount,the 8T cell with RMW sequence control could be better thanupsizing 6T cell in terms of the overall SRAM core area, asdiscussed in , , and .
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