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Table Of Contents

Verilog Abstraction Levels
Behavioral level
Register-Transfer Level
Gate Level
Block diagram of arbiter
Low level design
Code of module "arbiter"
Bi-Directional Ports Example -
Vector Signals Example -
Data Type
Examples :
History Of Verilog
Various stages of ASIC/FPGA
High Level Design
Micro Design/Low level design
RTL Coding
Place & Route
Post Silicon Validation
Hello World Program
Hello World Program Output
Counter Design Block
Counter Design Specs
Counter Waveform
Lexical Conventions
White Space
Examples of White Spaces
Functional Equivalent Code
Examples of Comments
Case Sensitivity
Examples of Unique names
Examples of legal identifiers
Escaped Identifiers
Numbers in Verilog
Integer Numbers
Example of Integer Numbers
Real Numbers
Example of Real Numbers
Signed and Unsigned Numbers
Transmission Gate Primitives
Switch Primitives
Logic Values and signal Strengths
Verilog Strength Levels
Example : Strength Level
B : Supply 0
Example 2 : Strength Level
A : Supply 1
UDP ports rules
TestBench to check the above UDP
Simulator Output
Arithmetic Operators
Relational Operators
Equality Operators
Logical Operators
Bit-wise Operators
Verilog HDL Abstraction Levels
Procedural Blocks
Example - initial
Procedural Assignment Statements
Example - Bad procedural assignment
Sequential Statement Groups
Example - sequential
Example - Parallel
Example - Mixing "begin-end" and "fork - join"
Blocking and Nonblocking assignment
Example - blocking and nonblocking
Example - assign and deassign
Example - force and release
Procedural blocks and timing controls
Delay Controls
Example - clk_gen
Simulation Output
Edge sensitive Event Controls
Example - Edge Wait
Level-Sensitive Even Controls ( Wait statements )
Example - Level Wait
Intra-Assignment Timing Controls
Example - Intra-Assignment
Example - Tri-state Buffer
Example - Mux
Example - Simple Task
Example - Task using Global Variables
Calling a Task
Example - CPU Write / Read Task
Example - Simple Function
Before you Start
Example - Counter
Code for Counter
Test Plan
Test Cases
Memory Modeling
Storing Values
Reading Values
Bit Read
Initializing Memories
Example - Simple memory
Example - Memory.list file
Parameter Override using defparam
Parameter Override during instantiating
Passing more than one parameter
Verilog 2001
What is logic synthesis ?
Life before HDL (Logic synthesis)
Impact of HDL and Logic synthesis
What do we discuss here ?
How it Works
Example - Hello World
C Code
Verilog Code
Running the Simulation
Comma used in sensitive list
Combinational logic sensitive list
Wire Data type
Register Data type
New operators
Signed shift operator
Power operator
Port Declaration
Assertions Languages
Advantages of using assertions
Implementing assertion monitors
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Published by Pradeep Babu

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Categories:Types, Research
Published by: Pradeep Babu on Apr 21, 2011
Copyright:Attribution Non-commercial


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