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Delayed Branching

Delayed Branching

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Published by BravoYusuf
This is a compiler-supported solution to control hazards. The idea is to let the compiler
rearrange the code so that a branch instruction’s effect is delayed by whatever number of cycles
required to discharge the dependencies. This is accomplished by placing such instruction(s) after
branch instruction that will execute regardless of branch is taken or not. Such instructions are
said to be in the branch delay slot.
This is a compiler-supported solution to control hazards. The idea is to let the compiler
rearrange the code so that a branch instruction’s effect is delayed by whatever number of cycles
required to discharge the dependencies. This is accomplished by placing such instruction(s) after
branch instruction that will execute regardless of branch is taken or not. Such instructions are
said to be in the branch delay slot.

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Published by: BravoYusuf on Apr 22, 2011
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10/24/2014

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CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_8
Page - 1 - of 4
Delayed Branching
This is a
compiler-supported 
solution to
control hazards
. The idea is to
let the compiler rearrange the code so that a branch instruction’s effect is delayed by whatever number of cyclesrequired to discharge the dependencies. 
This is
accomplished by placing such instruction(s) after branch instruction that will execute regardless of branch is taken or not 
. Such instructions aresaid to be in the
branch delay slot 
.
In MIPS example, we compute BTA and evaluate branch condition in the ID stage and hencesuffer 1 cycle penalty in case of misprediction (i.e. branch is taken while we guessed it to beuntaken). This suggests that in our example branch delay slot = 1 instruction. In pipelines where branch is tested later in the pipeline, branch delay slot may comprise multiple instructions.The behavior of MIPS pipeline employing delayed branching is shown in the following diagrams
.
The branch instruction is assumed to be
ith
instruction.
Untaken
branch instr 
IF ID EX M WB
Branch Delay Slot
Instr i + 1
IF ID EX M WB
Instr i + 2
IF ID EX M WB
Instr i + 3
IF ID EX M WB
Instr i + 4
IF ID EX M WB
Taken
branch instr 
IF ID EX M WB
Branch Delay Slot
Instr i + 1
IF ID EX M WB
Branch target
 
IF ID EX M WB
Branch target + 1
IF ID EX M WB
Branch target + 2
IF ID EX M WB
Schemes for Scheduling Branch Delay Slot(s)
The job of the compiler is to make the successor instructions (those in the branch delay slot)
validand
 
useful.
There are three delay-slot-scheduling schemes used in practice:a.
 
From Before Branch b.
 
From Targetc.
 
From Fall Through
a.
 
From Before Branch
Here the delay slot is scheduled with an independent instruction
 from before the branch
.This is
the best 
choice. Options b and c are exercised when this option is not possible
 
CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_8
Page - 2 - of 4
b.
 
From Target
 
CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_8
Page - 3 - of 4
In this code sequence, the use of $s1 in the branch prevents the add instruction (whosedestination is $s1) from being moved after the branch i.e. in the branch delay slot. Here, the branch-delay slot is scheduled from the target of the branch; usually the target instruction willneed to be copied because it can be reached via another path.
c.
 
From Sequential Fall Through
c. From Fall Through becomesTo make this optimization legal for (b) and (c), it
must be OK to execute the sub (i.e. theinstruction in the delay slot) instruction when the branch goes in the unexpected direction.
 OK means that the work done might be wasted but the program will still execute correctly.E.g. this is the case if $4 were an unused temporary register when the branch goes in theunexpected direction.
add $1, $2, $3if $1 == 0 thensub $4, $5, $6Delay Slotadd $1, $2, $3if $1 == 0 thensub $4, $5, $6

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