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Table Of Contents

Major FPGA vendors
Xilinx Point of Reference
CLB Structure of Spartan 3
Simplified Slice Structure
Detailed Slice Structure
SRAM Cell (Pass Transistor)
Look-Up Tables
Look Up Table (LUT)
Programmable Logic Block
FPGA Function generators
Fast Carry Logic
Accessing Carry Logic
Flexible Sequential Elements
Shift Register
Shift Register LUT Example
Distributed RAM
Xilinx Multipurpose LUT
Embedded Ram Blocks
Spartan-3 Block RAM Amounts
Block RAM Port Aspect Ratios
Dual-Port Block RAM
Dual-Port Bus Flexibility
Two Independent Single-Port RAMs
Embedded Multipliers
18 x 18 Embedded Multiplier
18 x 18 Multiplier
Positions of Multipliers
18-bit Multiplier with Register
Digital Clock Managers (DCM)
DCM: Jitter Removal
DCM: Frequency Synthesis
DCM: Phase Shifting
IOB Functionality
Configurable I/O Impedances
Spartan-3 FPGA Family Members
2001 –Virtex-II FPGA Family
Virtex II Pro Floorplan
Embedded Processor Cores (Hard and Soft)
Embedded Core (Inside)
Soft Core
Virtex Architectures
The Spartan-3 Family
Spartan-3 Family
Spartan-3E Features
Spartan-3A DSP Features
DSP48 Comparison
Spartan-3A Device Table
Architecture Alignment
Designers Eccentrics
Virtex-6 Logic Fabric
Higher DSP Performance
Spartan-6 CLB Logic Slices
Memory Controller
Integrated DSP Slice
Spartan-6 LX / LXT FPGAs
Timing report after synthesis
Map report header
Map report
Place & route report
Post layout timing report
Post-place-and-route simulation
System Gates vs. Real Gates System Gates vs. Real Gates
State-of-the-Art FPGAs
FPGA Shortcomings
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04 FPGA Updated

04 FPGA Updated

Ratings: (0)|Views: 2,178|Likes:
Published by Usman Zafar

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Published by: Usman Zafar on Apr 25, 2011
Copyright:Attribution Non-commercial


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