Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Save to My Library
Look up keyword
Like this
1Activity
0 of .
Results for:
No results containing your search query
P. 1
Summer Training in VLSIDesign - 2011

Summer Training in VLSIDesign - 2011

Ratings: (0)|Views: 111 |Likes:
Published by Devender Khari
This training program is directed toward skill building in Verilog & FPGA. This serves a good foundation for building a rewarding career in VLSI Industry.
This training program is directed toward skill building in Verilog & FPGA. This serves a good foundation for building a rewarding career in VLSI Industry.

More info:

Published by: Devender Khari on Apr 29, 2011
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

04/30/2011

pdf

text

original

 
Summer Training
(Four/Six/Eight Weeks)
 
in
VLSI Design
(RTL using Verilog
 
& FPGA)
 
 An Initiative by Industry Expertsfrom Cadence, Atrenta & Patni with qualification fromIITs and BITS-Pilani Training Partners of Cadence DesignSystems and Mentor Graphics(Worldwide EDA Giants)
DKOP Labs Pvt. Ltd.
Knowledge, Operations and PracticesC-53, Lower Ground Floor, Sector – 2, Noida – 201301Tel: 0120-4276796, 0120-4203797; Tel/Fax: 0120-4274237; Mob: +91-9971792797Email:info@dkoplabs.com; Web:http://www.dkoplabs.com 
 
MODULE TOPICS
 
Four weeks training will cover modules 1, 2, 3, 4, 5 & 10Six Weeks training will cover modules 1, 2, 3, 4, 5, 6, 7 & 10Eight Weeks training will cover modules 1, 2, 3, 4, 5, 6, 7, 8, 9 & 10
MODULE 1: VLSI DESIGN FLOWMODULE 2: ADVANCED DIGITAL DESIGN
1.
 
Design Concepts2.
 
Introduction to Logic3.
 
Optimized Implementation of Logic Functions4.
 
Number Representation and Arithmetic Circuits5.
 
Combinational-Circuits Building Blocks6.
 
Flip-Flops, Registers, Counters, and Simple Processor7.
 
Synchronous Sequential Circuits8.
 
 Asynchronous Sequential Circuits9.
 
Digital System Design10.
 
Testing of Logic Circuits11.
 
Computer Aided Design Tools
MODULE 3: VERILOG HDL
1.
 
Overview of Digital Design with VerilogHDL2.
 
Hierarchical Modeling Concepts3.
 
Basic Concepts4.
 
Modules and Ports5.
 
Gate-Level Modeling6.
 
Dataflow Modeling7.
 
Behavioral Modeling8.
 
Tasks and Functions9.
 
Useful Modeling Techniques10.
 
Timing and Delays11.
 
Switch-Level Modeling12.
 
User Defined Primitives13.
 
Programming Language Interface14.
 
 Advanced Verification Techniques
MODULE 4: BASICS OF TESTBENCHES
1.
 
Design Testing Concepts2.
 
Test Bench Generation3.
 
Simulation & Verification using Test Benches
 
3/10
MODULE 5: PROJECT IN VERILOG
1.
 
Project Study2.
 
Design & Implementation using Mentor Graphics ModelSim simulation tools3.
 
Presentation4.
 
Document submission5.
 
Evaluation of Project 
MODULE 6: FPGA BASICS
1.
 
FPGA Kit Introduction2.
 
Special FPGA Resourcesa.
 
Block RAMb.
 
DCM (Digital Clock Manager)c.
 
Dedicated Arithmetic functions3.
 
FPGA Kit interfacing and configurationa.
 
LCDb.
 
PS2 Mousec.
 
VGA Controllerd.
 
 A/D
MODULE 7: FPGA – MINI PROJECT
1.
 
Project Study2.
 
Design & Implementation using Xilinx FPGA kit and Xilinx Synthesis tools3.
 
Presentation4.
 
Document submission5.
 
Evaluation of Project 
MODULE 8: FPGA ADVANCED
1.
 
FPGA Kit interfacing and configuration – Advanceda.
 
PS2 Keyboardb.
 
RS232 serial interface (UART)c.
 
VGA Controllerd.
 
D/Ae.
 
External RAMf.
 
Onboard FLASH Memory & ROM2.
 
Configuring & Utilizing FPGA Resourcesa.
 
Global Clock Resourcesb.
 
LUT as Shifters & Distributed Memoryc.
 
Dedicated Arithmetic functions-Adder & Multipliersd.
 
Macro functions3.
 
Embedded FPGA Designa.
 
Using EDK in the project b.
 
Using Pico-Blaze/Micro-Blaze Soft Controller
MODULE 9: FPGA PROJECT
1.
 
Project Study2.
 
Design & Implementation using Altera high end FPGA Kit and Altera EDA tools

You're Reading a Free Preview

Download
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->