Professional Documents
Culture Documents
A Literature review submitted in partial fulfillment of the requirement for the degree of
Master 2 (Research): Micro & Nanoelectronics
By:
PIRZADO Azhar Ali Ayaz
I wish to express my sincere gratitude to my supervisor Dr. Fabien Prégaldiny for his
invaluable guidance and advice during every stage of this endeavor. I am greatly
indebted to him for his continuing encouragement and support without which, it
would not have been possible for me to complete this undertaking successfully. His
insightful comments and suggestions have continually helped me to improve my
understanding.
I thank Dr. Daniel Mathiot and Dr. Pattrick Leveque (InESS, CNRS) for their
discussion, encouragement and advice in the beginning of this work.
My special thanks to my parents and friends who were always there for me, to
constantly encourage and appreciate for the completion of this task.
To my beloved Jeena Khan, whose love always inspired me and taught me how to live
and strengthen my belief in my abilities.
iii
ABSTRACT
This paper attempts to study and review the Nanowire Junctionless transistors
(JNTs). We attempt to increase the predictive understanding of the device structure,
nature, operation characteristics and fabrication process by reviewing the literature.
Some comparisons with Bulk MOSFET and SOI-based Multi-gate FETs (MuGFETS)
are presented in order to analyse the performance of Junctionless transistors.
Finally, its suitability for Short-Channel Nanowire Junctionless Transistor design and
operations is assessed.
iv
TABLE OF CONTENTS
ACKNOWLEDGEMENTS..........................................................................................iii
ABSTRACT...............................................................................................................iv
TABLE OF CONTENTS..............................................................................................v
LIST OF ILLUSTRATIONS...................................................................................... ..vi
6. CONCLUSION................................................................................................22
7. Appendix: Permission(S)................................................................................23
8. References.....................................................................................................24
v
LIST OF ILLUSTRATIONS
vi
section of Si NW (b) TEM micrograph of cross-section pi (п) gate
gated-resistor (c).
Fig.19 Different effective gate lengths in: a junctionless transistor in the off 20
state (a), a junctionless transistor in the on state (b), an inversion-
mode transistor(c).
Fig.20 The electrical characteristics of 50nm JNT: Drain Current (ID) as 21
function of Gate voltage (VG) (a), Subthreshold Slope (SS) versus
Gate voltage VG (b).
Fig.21 The out put (ID - VDS) characteristic for SiNW junctionless transistor 22
dimensions shown in fig. 18 (a). n-type JNT doped by As impurity
atoms (a), p-type JNT doped by Ga impurity atoms (b)
vii
REVIEW OF SILICON NANOWIRE JUNCTIONLESS TRANSISTORS
1. INTRODUCTION
With the ever-increasing demand for scaling MOS devices and increasing
the integration density of MOS devices beyond Very Large Scale Integration
technology has led microelectronics research to cross the boundary from
micro (micrometer= 1 millionth of a meter, 10-6) to nano (nanometer= 1
billionth of a meter, 10-9) dimensions. Latest developments in Nanoscale
technologies and hybrid approaches to solve scientific and engineering
problems based on the Bottom-up and old Top-down have brought to the
attention many novel materials, properties, and devices and hence opened
the doors to solve various existing scientific problems in almost all fields of
science, engineering and technology [2].
1
alternate routes based on self-assembly and molecular transport. New
architectures would enhance performance and packing density by orders
of magnitude, improve the functional complexity of Integrated Circuits
(ICs), and operate at higher switching speeds. Nanometer scale devices and
organic molecules are investigated for unique possibilities such as
extremely low power dissipation, quantum effects, surface sensitivity and
low synthesis cost. The building blocks for future electronics, rooted in
nanoscale science, would aid in the continued advancement of integrated
circuit technology [2].
P-N junctions have played pivotal role in electronics for many years. These
pn junctions serve the most important part of functionality of
semiconductor electronic devices from diodes to transistors. Almost all
transistors and diodes rely on pn junctions for their operation by
exploiting various modes and types of junctions. Dependence of electronic
devices upon pn junctions for their operation (desired operation) over
decades has been so much compulsory that it seemed almost impossible
to realize the functionality of diodes or transistors without junctions. The
fact, that current-voltage characteristics of devices are controlled by the
presence, absence, magnitude and polarity of applied voltage and/or
electric field to pn junction electronic industry has spent considerable
amount of energy, effort, time and human resources to exploit the junction
phenomenon to optimum level. While this approach coupled with
improvements in Integrated circuit (IC) technology has given us greater
understanding of junctions and hence played its role, in helping to
continue, the progress in Integrated Circuits (ICs). The ever increasing
2
demand for high switching speed, computing power and huge storage
capacity have led electronics industry to scaling the geometry of
transistors. The continued scaling of geometry and parameters has
resulted in emergence of some problems like Short-Channel Effects (SCE),
tunneling of Gate oxide, Drain-Induced-Barrier-Lowering (DIBL) and
leakage effects which pose threat to further reduce the transistor
dimensions without sacrificing the performance or increasing the cost per
unit device in an IC. Thus, need for improving the present technology and
finding alternate device architectures was felt around two decades ago and
some unconventional devices like Double and triple gate Metal-Oxide-
semiconductor Field-effect Transistors (MOSFETS) using Silicon-on-
Insulator (SOI) technology have been made to improve the control of gate
over channel and minimize the SCEs [9,10,11]. Junctions are becoming
increasingly difficult to engineering with high doping as required for ultra-
short devices in nanometer scales. Good control of doping concentrations
with greater number of dopants in active condition requires high
temperature anneals. This results in increase in cost. A transistor without
junctions will not need costly anneal diffusion steps to be fabricated. It will
save energy, effort, time and most importantly money. A Junctionless
device also avoids some of the inherent problems associated with sharp
gradient changes in junctions and interfaces. Above all, the device design
becomes simpler as opposed to ever growing complexity with scaling and
increase in functionality and performance of devices.
The idea of transistor without junctions was proposed by Lilienfield in his
gated-resistor apparatus in 1925 [10], well before the invention of first
transistor in 1947. A team of researchers from Tyndall Institute have
demonstrated the fully-Complementary Metal-Oxide-semiconductor
(CMOS) capable Junctionless device made with Silicon Nanowire (SiNW)
using SOI technology which appeared in Nature in 2010 [11]. Few other
teams of researchers have also demonstrated similar type of devices with
different names but the operation principles remain essentially the same.
This tri-gate (or Gate-all-around; GAA) device has advantages in reduced
the problems faced by bulk Metal-Oxide-semiconductor Field-effect
Transistors (MOSFET) devices and matching performance profile with MOS
devices. Junctionless devices have opened new doors to continue the
shrinking of size of transistor in sub-micron scales and hence the potential
of these devices is being investigated and discussed here by topical review.
The search results from high impact factor journals reveal that, during
past six months (July to Dec, 2010), research papers on Junctionless
devices is increasing. As many as 15 papers in IEEE, Elsevier
Sciencedirect, Nature Nanotechnology, and Applied Physics letters
appeared on this device.
3
1.3. NATURE AND STRUCTURE OF TRANSISTOR
4
by Tyndal team; Jean Pierre Colinge and his colleagues/co-authors [11] is
focused here for review due to following reasons:
5
is also shown to separate the Gate from channel. For closer description,
the device is illustrated in figure 2 in order to appreciate the small
geometrical scales and dimensions with Transmission Electron Microscope
(TEM) image coupled with schematic of the device. This isolation is
necessary for controlling the electric field and hence the amount of current
in the channel. The Gate voltage controls the current.
For p-channel device, only Si NW is doped with P+ impurities and the gate
is of N+ polysilicon. Figure 3 shows both cross section of both N-Channel
(A) and P-channel (B) of Gated-resistor or JNT [11].
Blue colour indicates strong p-type (acceptor) doping by BF 2 and light blue
colour represents the heavy doping by n-type material As (donor). Green
indicates gate oxide or SiO2.
6
1.4. THE CHARACTERISTICS OF JUNTIONLESS NANOWIRE
TRANSISTOR.
The Nanowire body becomes channel itself. The Channel keeps expanding
as we pass the Vth and beyond till flat-band conditions are reached; figure
4D. After reaching Flat-band voltage (VG=VFB) level, the device is in flat-
band conduction [11].
In normal device operation, the influence of Drain Voltage counts more for
on-current of the device so we explain the effect of VD with VG held
constant at VG greater than Vth [2]. As VD is increased gradually, the gated-
resistor is driven into saturation in the same manner as bulk MOS
7
transistor. This is illustrated in figure 5 below. The amount of drain
current ID that results from increased VD is on-current (ION).
8
gated resistors Si NW width, W is 20nm and the length of gate is 1 µm.
The W/L ratio is 0.02.
9
2 RECENT RESEARCH RELEVANT TO THE JUNCTIONLESS DEVICES
(a) (b)
Figure 9: Bulk MOSFET with junctions (a) and SOI Junctionless transistor
(b) [21, 25]
Since the channel is homogeneously doped n-type for n-channel (or p-type
for p-channel) so it helps solve the problems that resulted from doping
gradients and statistical variations in doping and costly annealing issues:
Short-channel effects (SCEs), gate oxide thickness (e.g. gate tunneling,
etc.), junction depth and dopant density fluctuation.
The JNT has gate from 3 edges, so it is a 3-gate SOI device. This tri-gate
structure is especially useful to give the gate greater control over the
channel. Hence it limits the SCEs. Figure 10 [25], shows the evolution
from single gate to tri-gate and/or gate-all-around architectures for
conventional thin-film-SOI devices with junctions. The gate structure in
conventional SOI devices and Junctionless transistors is similar. Second
advantage of having no junctions is that there is no gradient change and
hence no diffusion takes place in JNT. Thermal budget and high
10
temperature anneals are excluded which saves energy, time and cost of
fabrication. This also serves as bases for fabricating the devices even with
shorter channel lengths since JNT doesn’t need the ultra-sharp doping
concentration gradients for switching between n-type and p-type (typical
values for doping concentration from n-type 1x1019 cm-3 to p-type 1x1018
cm-3). This shift of concentration within small distance has been a
constant challenge for short-channel devices. [11]
Where COX is the gate oxide capacitance (ox/tox), W is the device width, L is
the gate length. Adding the gate electrode capacitance, C= COX WsiL (Wsi =
W) to this equation, we can calculate the intrinsic time delay of
conventional device:
(2)
(3)
(4)
12
Notice that there is no change in the capacitance of the gate electrode in
both devices; Bulk MOS and gated-resistor [11]. Figure 12 shows
comparison between conventional MOSFETs and Gated-resistors with
different doping concentrations, on the basis of intrinsic delay. Notice the
gate delay (CV/I) given in picoseconds (ps) increases with an increase in
gate length in nanometers (nm) in both devices but decreases by
increasing the doping concentrations in gated-resistors. Hence, speed
(intrinsic delay) becomes independent of gate-oxide thickness. This is good
news that the efforts needed to continually decrease effective oxide
thickness (EOT) will not be necessary any more [19]. In figure 12, EOT is
equal to 1 nm for all gated resistors, and further it can be assumed that Tsi
equals L [11]. Looking at different curves in the figure, which correspond
to channel doping levels, as low as 1x1019 cm-3 to as high as 8x1019cm-3,
one can clearly appreciate the amount of improvement brought to
performance by increasing doping [11].
13
Figure 12: Comparison of intrinsic delay time in Bulk MOS and Gated-
resistors. Comparison of different doping concentrations in gated-resistors
is also shown.
14
simulations [14] in figure 14 show clearly the dependability of Vth on WSi
and doping.
(5)
Figure15: ID saturation in JNTs with WSi = TSi and L=25 nm, Tox =1nm and
a poly+ polygate is used. VDD =1V and Ioff=100nA/um (a), ID saturation in
JNTs with TSi= 2xWSi and L=25 nm, Tox =1nm and a poly+ polygate is
used. VDD =1V and Ioff=100nA/um (b) [12].
15
3. SUBTHRESHOLD SLOPE (SS) AND DRAIN INDUCED BARRIER
LOWERING (DIBL) IN JUNCTIONLESS NANOWIRE TRANSISTORS
As explained earlier (please refer to figure 7 at page number 9), the Ion/Ioff
of gated-resistors is higher than 1x106 [11]. The superior behaviour of
device for subthreshold Slope (SS) and drain-Induced Barrier Lowering
(DIBL) is a key merit for gated-resistors. The SS defines how sharply a
device can switch from one state to another (on-off switching). Expressed
in mV/decade, the SS can be drawn as the inverse of the slope of ID (log)
versus VG below Vth. Gated-resistors demonstrate SS of 64mV/dec at
300K. The variation with temperature values of 225 to 475K remain fairly
close to the ideal lower limit (kBT/q) ln(10) [11]. This compares well with
numerical values of SS 63 mV/dec for best conventional SOI tri-gate
transistors and is much better then 80 mV/dec for classic Bulk transistors
[11,27]. To further understand the electrical characteristics of junctionless
transistor, we present the comparisons between junctionless and classical
SOI-based multi-gate (MuGFETs=Double-gate or Tri-gate TFTs) Inversion
Mode (IM) devices in figure 16 (a) and (b) [3]. For these simulations, the
effective channel length of IM devices is 8 nm (as opposed to original
physical channel length of 10nm due to S/D and S/G overlaps). Channel
doping is kept low in order to avoid corner effects [28].
The leakage current IOFF in junctionless device is well below the IOFF for IM
transistor (around 10-15) as the shown in figure 16(a) which plots ID as
function of VG. The DIBL is less than one-third the value observed in IM
devices. Figure 16(b) compares the results for two types of devices,
showing how DIBL and Vth vary with physical gate length (Lgate) [13]. This
figure plots DIBL by measuring the variation in Vth with change in VD from
50 mV to 1V. Hence the variation in Vth as function of VDS (DIBL = Vth(VDS
= 0.05 V)- Vth(VDS = 1 V)) [13]. These plots clearly establish the suitability
of Junctionless transistor for short channels as it is evident from looking
at DIBL and Vth values at 10 nm Lgate.
16
Figure 16(a): Id–Vg characteristic of Figure 16(b): DIBL and
a junctionless device and an threshold voltage of junctionless
inversion-mode device with Lgate = and inversion-mode devices as a
10 nm [13]. function of physical gate length
[13].
17
concentration can start from 2x1019 cm-3 and can go as high as 5x1019
cm-3. The impurity materials are Arsenic for N-type and BF2 for P-type
devices. Full depletion is necessary for turning the device off
electrostatically. Small cross-sections make depletion easier to achieve.
Once doping is performed, gate structure is formed. A layer of amorphus
silicon with thickness of 50 nm is deposited in low-pressure chemical
vapour deposition (LPCVD) reactor at 550°C to form the gate. Gate is then
heavily doped with Boron or Arsenic ion impurity to form opposite doping
polarity with channel. N-type gate with Arsenic impurity profile of 2x1014
atoms per centimetre square (cm-2) for p-channel device, for example.
Boron is used (to dope the gate) for n-channel device. To activate the
dopant impurities by transforming amorphus to polysilicon, annealing is
performed for 30 min at 900°C in nitrogen. Contact electrode for gate is
patterned by oxide deposition and etching in reactive-ion etch (RIE)
reactor. Transmission electron microscope images of five parallel silicon
gated resistor nanowires/nanoribbons with a common polysilicon gate
electrode are illustrated in the figure 17. Image of individual nanowire is
magnified in Figure 17b for the sake of details. The oxide is deposited and
etched to form contact holes after the gate electrode. Finally, the
metallization by aluminium plus TiW is done thereby finising the process
by establishing the electrical contacts to the device terminals/ electrodes.
This device has the gate electrode wrapping from two sides and top of
channel (along three edges) so we call it multi-gate, tri-gate, or gate-all-
around device [11,26]. The major difference in the fabrication process
from classical trigate FETs is that: the channel of classical tri-gate is
either is left undoped or doped with p-type material at a concentration of
2x1017 cm-3 for n-type device. A heavy doped N+ Polysilicon is used as
gate. The source and drain junctions are formed using Arsenic doping by
ion-implantation (dose= 2x1014 cm-2 with an energy of 15 keV) [11].
18
5. POTENTIAL FOR SCALING
19
Figure 18: The structure, geometry and cross section of short-channel
Junctionless transistors. A 3 nm gate device structure (a), cross section of
Si NW (b) TEM micrograph of cross-section pi (п) gate gated-resistor (c)
[17,20].
In principle, gate length can scale with wire thickness, without reducing
the gate dielectric thickness [29].
The other issue of doping is important in Nanowire Junctionless devices
with short channels and/gates. Although, Junctionless device is without
junctions (hence no dopant gradient from junctions to channel) but heavy
doping is required for channel, source and drain. Therefore, the doping
concentration (and positioning of dopants) becomes critically important at
short channel lengths of few nanometers [24]. Localisation of dopants is
required to near perfect in order to avoid variations in V th from device to
device. As we have already seen above that highly doped channel make Vth
sensitive to WSi or in other words, Vth variations are due WSi (high doping).
SHORT-CHANNEL EFFECTS
20
increased due to the presence of Space Charge Zone (SCE) and DIBL (L OFF
< LON). Figure shows how the length of device plays role at different times:
when the device is on and when it is off. For bulk MOSFETs, the Physical
length Lphysical is the actual designed length of channel, Leff the effective
length when device is on and LSCE is the effective length when the device is
off [20].
This is illustrated in figure 20. The graphs show the. Drain Current (ID) for
a 50 nm device as function of Gate voltage (VG) is shown in (a), and the
Subthreshold Slope (SS) versus Gate voltage VG is depicted in (b) [20].
It is apparent from the figure 20 that we have: (a) high on-off ratio (106), (b)
very good SS (60 mV/dec) and DIBL (7 mV) characteristics are achieved.
Absence of junctions and squeezing of device electrostatically makes these
results possible.
Figure 20: The electrical characteristics of 50nm JNT: Drain Current (ID) as
function of Gate voltage (VG) (a), Subthreshold Slope (SS) versus Gate
voltage VG (b) [20].
The out put characteristics (ID - VDS resulting from simulations) for 3nm
gate junctionless device are shown in figure 21 (a) and (b) for n and p-
channel respectively. This device shows good behaviour in saturation and
can be used in constant-current source applications [17].
21
Figure 21: The out put (ID - VDS) characteristic for SiNW junctionless
transistor dimensions shown in fig. 18 (a). n-type JNT doped by As
impurity atoms (a), p-type JNT doped by Ga impurity atoms (b) [17].
6. CONCLUSION
22
7. Appendix A: Permission(s).
Hello/Bonjour,
http://www.tyndall.xxxxxx/xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
JPC
---------------------------------------
Prof. Jean-Pierre Colinge
Tyndall National Institute
Lee Maltings, Dyke Parade
Cork , Ireland
Tel.: +353 21 490 48 65
Fax.: +353 21 490 42 97
23
8. REFRENCES
[4] Choi, Y.K. et al, “Nanoscale CMOS spacer FinFET for the terabit
era”, IEEE Elect. Dev.Lett. 23. 25–27(2002).
[5] Yu. B. et al, “Scaling FinFET to 10 nm gate length”, IEDM Tech Dig.
251–254. (2002).
[9] Sze, S.M., “Physics of Semiconductor Devices”, 2nd Ed., John Wiley
and Sons (WIE), USA, ISBN 0-471-33372-7, 2002, pp. 84-104.
[14] Weis, M. et al, “Low power SRAM cell using Vertical Slit Field Effect
Transistor (VeSFET)”, ESSCIRC Fringe P6 (2008).
24
[15] Sore´e, B. et al, “Silicon nanowire pinch-off FET: basic operation and
analytical model”. Proceed. of Ultimate Integration on Silicon
Conference (ULIS) 18–20 Poster 249 (2009).
25
[27] Colinge, J. P. et al, “Analytical model for the high-temperature
behaviour of the subthreshold slope in MuGFETs”, Microelectron.
Eng. 86, pp. 2067–2071 (2009).
[28] Fossum, J.G., Yang J.W., Trivedi V.P., “Suppression of corner effects
in triple-gate MOSFETs. IEEE Elect. Dev. Lett. 2003;24(12):745–7.
26