VO LU M E 3 ISSUE 1
SemiCon Times
FEB 7th 2011
Inside This Issue
1. Front-End Design Knowledge and Skills
2. Importance of System Verilog
3. Mentor Graphics HEP Training
4. Summer Training – 2011
5. Knowledge Base for a Computer
Science Engineer
6. Linux Tools and Utilities
7. Industry Watch – nSys Design System
8. News & Updates
9. Placement News
10. News & Events at DKOP Labs
DKOP Labs Pvt Ltd, C-53, Sec-2, Noida,
Front-End Design - Knowledge and Skills
The following is a list of the most important skills and
knowledge that an aspiring front-end digital designer must
acquire and master
-Digital Electronics
-Microprocessor Design
-Computer Architecture
- Modeling and Verifying Designs using simulation - Verilog,
VHDL
-High level Verification – SystemVerilog, SystemC
-Formal Verification - Equivalence Checking, Model
Checking
-Timing Analysis - Static and Dynamic
-Logic Synthesis, Behavioral Synthesis
-Design for Test - test-vector generation, fault simulation,
scan based design
Some of the above is pure knowledge - and can be
acquired from books and papers. A lot of the above needs
an engineer to acquire new skills, use new tools and utilities,
adopt new design methodologies - which can happen only
by constant practice and hard work, training and
apprentice-ship.
The Importance of SystemVerilog
Most electronics engineers are adept at Verilog, the
dominant hardware description language of the last 2+
decades. An easy language to learn and use, engineers
can become comfortable with it within 1-2 weeks, and
experts within a few months.
However, in industrial settings of today, the original Verilog
language would have been severely inadequate. It lacks
scores of features necessary to design and verify the large
designs of today.
In fact, for several years, VHDL rose to prominence
precisely because it offered a variety of constructs that
would allow designers to specify complex objects and
relationships, as also build complex test-benches and
levels of abstraction. These were all absent from the
original Verilog.
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PAGE 2 SEMICON TIMES

SystemVerilog started with the donation of the Superlog

language and the OpenVera functionality from Synopsys.
It became an IEEE standard in 2005.

The feature-set of SystemVerilog can be divided into two

distinct roles
- SystemVerilog for RTL design
- SystemVerilog for verification

The kind of constructs that were added were

- new data types - enumerated types, new integer types,
structures, unions, strings, classes, dynamic and associative
arrays, queues
- procedural blocks - always_ff, always_comb,
always_latch
- priority/unique if/case - to aid synthesis
- interfaces
- randomization methods, constrained random generation
- sequential and concurrent assertions
- constructs for measuring and reporting coverage
- constructs for synchronization - semaphores, mailboxes

Additionally, existing operators in Verilog acquired

powerful new usages.

All major EDA vendors (Mentor, Cadence, Synopsys)

support a large part of this new standard in their simulators
(ModelSim/Questa, NCSim, VCS).

As a result of the adoption of this new subset as an IEEE

standard, the growing support from EDA vendors, and its
inherent power and functionality, a large number of
electronics companies are using SystemVerilog for the
design and verification of complex chips and systems.

Any engineer entering the workforce today must get

acquainted with this new emerging standard, and
enhance his/her skill-set and knowledge.

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796
SEMICON TIMES PAGE 3

Mentor Graphics is MENTOR GRAPHICS HEP TRAINING-2010

One of the largest
30 students, graduated from 25 different schools. Chosen to
EDA Companies
undergo Mentor's “Verification Engineer” training program as
In the world. part of its HEP (Higher Education Program) initiative. The task –
use an NCSU (North Carolina State University) developed
course to teach the chosen 30 students “System Verilog for
Verification”.

This meant teaching them System Verilog constructs needed

for verifying a design, and use all of those in verifying a given
design. The design was a pipelined 16-bit microprocessor, the
LC3, often used in universities for teaching various courses. The
functional parts of this design had been protected, so the
whole DUT was a black box for the students. The design had
been infused with tens of bugs, each of which could be
turned on and off by the instructors. Each student had a
different set of bugs, and the objective was to find all bugs
using System Verilog testbenches.

The course involved teaching them new data types (queues,

associative and dynamic arrays, structures, enumerated types
and strings), interfaces, procedures, object oriented
programming, randomizations, threads, interprocess
communication and building verification environments.

This was an intensive 30 days course, of 8 hour days. The

lectures took 52 hours, the labs and assignments another 48,
and the two projects were spread over 144 hours. The course
spanned 6 weeks, a much more compressed version than
what is offered to students at NCSU, who do the same over a
20 week period.

The element of competition - “who finds all their bugs the

fastest” - turned the entire course into an intense game.
Almost as soon as the students learned and played with the
new constructs using specific small targeted labs, they also
ramped up on the microprocessor specifications. For most of
them, reading a lengthy specification of that size was also a
first.
The first few bugs could be found by focused and directed
testbenches, but the bugs that had been introduced were
such that only a set of random inputs could find them fast
enough. The students were thus forced to use all the new tools
in their command – structures, queues, interprocess
communication, constrained randomization, sequential and
concurrent assertions, and enumerated types – the whole
gamut of System Verilog constructs and methodologies
covered in the course.

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796
PAGE 4 SEMICON TIMES

It was observed that the directed goal – finding bugs – made

the learning of System Verilog almost a corollary. Contrary to
our observations in other courses, where students retain a small
percentage of the course, this course forced students to use
almost all of what had been taught. For many of them, the
most difficult part was the object oriented aspects and the
assertions. Anticipating some of this, we added a host of labs to
the standard NCSU course. This added to the hours, but made
the latter part of the course – the project – easier to master.

Most students were able to find all the bugs in the first project –
this had a non-pipelined version of the processor. The second
project – with pipelining – was more challenging. It had more
pernicious and hard-to-find bugs, running into multiple cycles,
discoverable only with specific sequences of microprocessor
instructions. This is where constrained randomization showed its
true powers, and where students could observe the power of
the constraints solver within Questa. Students used coverage
assertions, metrics and score boards to get a sense of how near
they were to completion.

Within a short span of 6 weeks, students learned a whole new

set of Verilog constructs, and how to use them to solve specific
problems, all inside the powerful Questa verification
environment – and made them all the more ready to venture
out and verify the big bad designs the world had for them.

Summer Training 2011 – Registrations Open

Registration for Summer Training -2011 is open now. The summer

training is available in three different domains:
Get yourself
1. Summer Training in VLSI Design Registered for Summer
Training before all the
2. Summer Training in Embedded Systems Design seats are taken!!

3. Summer Training in Software Development Act Fast!!

For Details please visit http://designkop.org/summer_intrenship.php

Attractive Early Bird Offers

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796
SEMICON TIMES PAGE 5

Knowledge Base for a

Computer Science Engineer

Why, oh why, do we do all these courses at college,

asked one student. Do we ever get to use them? He
rattled off the entire list -
• Discrete Maths, Automata Theory,
Computational Complexity
• Data Structures (DS), Design & Analysis of
Algorithms (DAA), Graph Theory
• Programming Languages, OO Techniques,
Compilers
• Operating Systems, Database Systems,
Networks
• Digital Logic, Computer Organization,
Microprocessors
• Computer Graphics, Web Technology, Software
Engineering,
• Image Processing, Distributed Systems, Artificial
Intelligence
• Parallel Algorithms, NLP, Computational
Geometry, Security
• Distributed Databases, Neural Nets, Embedded
Systems

These are the same courses that get done at IIT, or MIT,
or CMU. All CS undergraduate in these top-rung
colleges do these courses, so it definitely makes sense
for students in other colleges to do them.
But why? We look at some common problems
programmers face in a real-life job, and find that these
courses play a significant part in the solution of these
problems.
• When dealing with performance and capacity
challenges – you need DAA, DS, Automata
Theory & Complexity Theory
• When evaluating whether a problem can be
solved at all, you again use DS, DAA,
Complexity Theory, Discrete Maths
• Porting a product to a multi-processor or a
network of processors, you would use Software
Engineering, Parallel & Distributed Techniques
The CS course syllabus is a very practical one – you will
get to use more than 80% of it in a job, provided you
are working on cutting edge stuff.
So, don't ignore these, thinking it is all “just theory”.
Master the fundamentals and you get to master your
destiny.

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796
PAGE 6 SEMICON TIMES

Linux Tools and Utilities

A student of computer science becomes a software
engineer by becoming skilled, which involves Turning
Knowledge into Tangible Results. The kind of skills that
are important are the following
• Design, Programming and Testing Skills
• Performance/Capacity Tuning, Quality
Metrics, Processes, Documents
• Code Organization, Traceability, Traversal
• Frameworks, compilers, debuggers, editors
• Memory Debugging, Code Coverage, Static
Analysis, Code complexity analysis
• Tools for code and test generation
•
In the final analysis, becoming skillful involves
improving ones personal ability, quality and
productivity.

How does one know one is skillful?

• You do things fast, easily
• It appear “elementary” to observers
• The finished product evokes a “wow”
• It is smooth and friendly, well tested
• You use some nifty tools
• You regularly get some amazing results
• You seem to walk on water!

A list of tools that one should learn and use -

• editors - vi, emacs
• environments - eclipse, anjuta
• code generators - flex, bison
• compilation/debugging - gcc, gdb, make,
as, ln, ldd, ar, nm, ranlib, objdump, valgrind,
mtrace, imake, autoconf, strings
• coverage – gcov
• version control - rcs, cvs, svn, git
• sharing code and documents – dropbox
• understanding & traversing code - ctags, diff,
grep, indent, cxref, cscope
• source code documentation – doxygen
• code release - rpm, shell scripts
• build/test automation - shell scripts, buildbot
• grid s/w for distributed testing – gridEngine
• static code analysis - gcc -Wall (lint), frama,
splint
So, fire up your favorite operating systems (Ubuntu!),
download all of these tools, and start using them.

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796
 SEMICON TIMES PAGE 7

Industry Watch – nSys Design Systems Pvt. Ltd

In this issue, we profile one of the prominent MNC set up in India – nSys
Design Systems Pvt. Ltd

Nature of Operations – nSys leverages the world’s largest portfolio of

Verification IPs it has developed, to provide products & services to
Accelerate Designs of its customers developing ASIC, FPGA or IP.

Some prominent products from nSys Design Systems Pvt. Ltd

are:
PCI-Family, ARM AMBA, SAS, SATA, ATPI, ETHERNET, USB3.0, USB2.0,
DDR2, DDR3, UART, SMBus.

Yearly Revenues (global) -

India operations – founded in 2001 nSys has offices in Newark, CA
and New Delhi. Get yourself Industry
Ready for building a
Size of India operations – 100+
career in core industry
Nature of work in India – Almost the entire gamut of activities of nSys
Design Systems Pvt. Ltd are dependent in one way or another at the
India operation. In a way, it is a microcosm of the global operations.

Kind of people hired – electronics engineers and software engineers

Desirable functional expertise for electronics engineers - Hardware

Description Languages (mainly Verilog and System Verilog),
Analog/Digital/RF design experience for PCB/Chips/Systems, scripting
languages such as Perl/TCL, Linux/UNIX

Work Environment – Innovation is the key here. Flexible work timings,

connectivity from home, a charged environment where fun is given
equal importance. "A playground for geniuses", as they put it.

External view of nSys Design Systems Pvt. Ltd in India – One of the
most innovative and respected MNCs in India. One of the top "best
places to work".

How does an electronics engineer prepare for a job here – mastery of

digital electronics and/or Computer Science; thorough understanding
of Verilog and System Verilog (VHDL is a much less important
requirement); understanding of Verification, Synthesis and Timing
Analysis; experience with EDA tools; fluency with Linux, Perl/TCL, C,
C++.

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796
PAGE 8 SEMICON TIMES

Industry News & Updates

1. Accellera Approves New Version of Electronic Design
System Modeling Standard
Source: edacafe, Jan,28 2011 www.edacafe.com
Accellera, an Electronic Design Automation (EDA)
standards organization, announced today that its Board
of Directors approved a new version of Accellera's
Standard Co-Emulation Modeling Interface (SCE-MI)
specification as a new Accellera verification standard.

2. Now, swipe smartphone to pay shopping bills

Source: indiatimes.com,Jan 28 2011
www.timesofindia.indiatimes.com JANUARY 2011
Technology will now enable people to make purchases S M T W T F S
by swiping their mobile phone across a till scanner-to be 1
rolled out this summer. 2 3 4 5 6 7 8
9 10 11 12 13 14 15
Consumers will be able to buy cinema tickets, a sandwich
16 17 18 19 20 21 22
or cup of coffee without the need for a card or cash.
23 24 25 26 27 28 29
30 31

Placement News FEBRUARY 2011

DKOP Students, who have completed their training in S M T W T F S
December, 2010 have been placed as follows: 1 2 3 4 5
1. Pankaj Talwar – nSys Design System 6 7 8 9 10 11 12
2. Richa Chuttani –nSys Design System 13 14 15 16 17 18 19
3. Parvinder Pal – Circuit Sutra
20 21 22 23 24 25 26
4. Balveer Singh –Cadence Design System
27 28
5. Nitin Ahuja – AgniSys
6. Vikas Tomar – Mentor Graphics
7. Amitav Banerjee – DKOP LABS Pvt Ltd. MARCH 2011
8. Jitendra Aggarwal - DKOP LABS Pvt Ltd. S M T W T F S
1 2 3 4 5
6 7 8 9 10 11 12
13 14 15 16 17 18 19
20 21 22 23 24 25 26
27 28 29 30 31
News and Events at DKOP LABS
1. DKOP is conducting training at MENTOR GRAPHICS
NOIDA for their employees. The training is focused on
Design, Analysis and Optimization of Algorithms.

2. New Industrial Training and PG Certificate Batch has

started on January 3rd.

3. New Website http://www.dkoplabs.com to be

available soon.

DKOP Labs Pvt Ltd, C-53, Sec-2, Noida, www.designkop.org, 9971792797, 01204203797, 4276796