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Qualitative Analysis of Hardware Description Languages: VHDL and Verilog

Qualitative Analysis of Hardware Description Languages: VHDL and Verilog

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Published by ijcsis
The field of electronics has, in the recent decades witnessed unprecedented, explosive and exciting progress. Several monumental changes have occurred in the design structure and execution of electronics principles. In the design process the functionality is defined through Hardware Description Language (HDL) especially Very High Speed Hardware Description Language (VHDL) and Verilog. A single chip is modeled by a large number of solid state devices and integrated circuits incorporating millions of active devices, these devices can be developed by using HDLs. VHDL on the other hand is evolved by incorporating and integrating ADA and Pascal language whereas Verilog is based on C language. These languages differ in different aspects bring a large differences between them in terms of their content, structure, reusability, portability, cost and so on. These differences also produce implementation issues. A comparison of the distinguishing characteristics in their entire ramification would help to frame future research in the field of electronics. In this direction, this paper attempts on an analysis of these languages will also help us to determine the relative superiority among these languages.
The field of electronics has, in the recent decades witnessed unprecedented, explosive and exciting progress. Several monumental changes have occurred in the design structure and execution of electronics principles. In the design process the functionality is defined through Hardware Description Language (HDL) especially Very High Speed Hardware Description Language (VHDL) and Verilog. A single chip is modeled by a large number of solid state devices and integrated circuits incorporating millions of active devices, these devices can be developed by using HDLs. VHDL on the other hand is evolved by incorporating and integrating ADA and Pascal language whereas Verilog is based on C language. These languages differ in different aspects bring a large differences between them in terms of their content, structure, reusability, portability, cost and so on. These differences also produce implementation issues. A comparison of the distinguishing characteristics in their entire ramification would help to frame future research in the field of electronics. In this direction, this paper attempts on an analysis of these languages will also help us to determine the relative superiority among these languages.

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(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011
Qualitative Analysis of Hardware Description Languages: VHDLand Verilog
R.Uma
Electronics and Communication EngineeringRajiv Gandhi College of Engineering and TechnologyPuducherry, Indiauma.ramadass1@gmail.com
R.Sharmila
Electronics and Communication EngineeringRajiv Gandhi College of Engineering and TechnologyPuducherry, Indiasharmeecool@gmail.com 
 Abstract 
 — 
 
The field of electronics has, in the recent decadeswitnessed unprecedented, explosive and exciting progress. Severalmonumental changes have occurred in the design structure andexecution of electronics principles. In the design process thefunctionality is defined through Hardware Description Language(HDL) especially Very High Speed Hardware Description Language(VHDL) and Verilog. A single chip is modeled by a large number of solid state devices and integrated circuits incorporating millions of active devices, these devices can be developed by using HDLs.VHDL on the other hand is evolved by incorporating and integratingADA and Pascal language whereas Verilog is based on C language.These languages differ in different aspects bring a large differencesbetween them in terms of their content, structure, reusability,portability, cost and so on. These differences also produceimplementation issues. A comparison of the distinguishingcharacteristics in their entire ramification would help to frame futureresearch in the field of electronics. In this direction, this paperattempts on an analysis of these languages will also help us todetermine the relative superiority among these languages.
 Keywords- HDL, VHDL, Verilog, performance evaluation
I.
 
I
NTRODUCTION
The word digital has made a dramatic impact on our society.More significant is a continuous trend towardscommunication, business transactions, traffic control, spaceguidance, medical treatment, weather monitoring, the internetand many other commercial, industrial and scientificenterprises. Development of such solutions has been possibledue to good digital system design and modeling techniques.In electronics, a Hardware Description Language or HDL is alanguage for formal description of standard text-basedexpressions of the spatial and temporal structure and behaviorof electronic systems. It describes the behavior of an electroniccircuit or system from which the physical circuit or system canthen be attained. The principal feature of a HDL is that itcontains the capability to describe the function of hardwareindependent of implementation. A HDL is analogous to asoftware programming language, but with major differences.Many programming languages are inherently procedural(single-threaded), with limited syntactical and semanticsupport to handle concurrency. HDLs, on the other hand,resemble concurrent programming languages in their ability tomodel multiple parallel processes (such as flip-flops, adders,etc.) that automatically execute independently of one another.HDLs have two purposes. First, they are used to write a modelfor the expected behavior of a circuit before that circuit isdesigned and built. The model is fed into a simulator, whichallows the designer to verify that the design behaves correctly.Second, they are used to write a detailed description of acircuit that is fed into a logic compiler. The output of thecompiler is used to configure a programmable logic devicethat has the desired function. Often, the HDL code that hasbeen simulated in the first step is re-used and compiled in thesecond step. There are many proprietary HDLs in use today,but there are only two standardized and widely used HDLs:Verilog and VHDL.The organization of the paper is as follows: the section 2,describe the background information of the VHDL andVerilog. The section 3, describes the HDL design flows. Thesection 4, presents the analysis of the VHDL and Verilog withvarious parameters like capability, constructs, data types, low-level modeling, high-level modeling, operators, library,forward-backward annotation, timing variables, procedure andtasks, compilation and commercial aspects are broadlydistinguished between VHDL and Verilog.II.
 
BACKGROUND
 
VHDL:
VHDL was developed by committee intended fordocumenting digital hardware behaviorally. The requirementsfor the language were first generated in 1981 under the VHSIC(Very High Speed Integrated Circuit) program as part of a USDOD (Department of Defense) project. In 1983 the DODawarded a contract with a team of three companies, IBM,Texas Instruments, and Intermetrics to develop a version of the language. It was known as VHDL 7.2 and was completedin 1985. Consequently, the language was transferred to theIEEE for standardization in 1986. After a substantialenhancement to the language it has become IEEE standard1076 in 1987 [1]. The deficiencies of this language lack in themodeling of gate and transistor level and there was no facilityfor handling timing information. But due to the lack of ASIClibraries and slower gate level simulation performance, peopleuse VHDL mainly for behavioral simulation, then synthesizeor translate the design to another simulation environment torun gate level sign-off simulation. The design communityproposed a methodology to help VHDL move towards a more
127http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011
useful design language. This initial effort was called theVHDL Initiative Towards ASIC Libraries, or VITAL 2.2B isdesigned to solve this key problem.
Verilog:
The Verilog HDL was first developed by GatewayDesign Automation in 1983 as a hardware modeling languagefor their simulator product. When cadence purchased theVerilog assets from Gateway in 1989, Verilog HDL andsimulation tools became popular and gained acceptance as ausable and practical language by a number of designers. In1990 Verilog HDL was placed into public domain and sincethen end-users, semiconductor companies and EDA(Electronic Design Automation) companies have directlybenefited from this open availability. In the same year OpenVerilog International (OVI) was formed to promote Verilog.They have improved the Verilog HDL documentation set andenhanced and extended the language for use with newtechnologies. In 1992, OVI decided to pursue standardizationof Verilog HDL as an IEEE standard. In 1995 the languagewas standardized by IEEE [IEEE Std 1364-1995] [2].III.
 
HDL DESIGN FLOW
 
Figure 1 HDL Design Flow
In any design, specifications are written first, specificationsdescribe abstractly the functionality, interface and overallarchitecture of the digital circuit to be designed. The next stepin evolving the design description is to describe the circuit interms of its behavior. The design at the behavioral level is tobe elaborated in terms of known and acknowledge functionalblocks. It forms the next detailed level of design description.Once again the design is to be tested through simulation anditeratively corrected for errors. The elaboration can becontinued one or two steps further. Logic synthesis toolsconvert the RTL description to a gate-level netlist. A gate-level netlist is a description of the circuit in terms of gates andconnections between them. Synthesis is a process by which anabstract form of desired circuit behavior (typically registertransfer level (RTL)) is turned into a design implementation interms of logic gates. Logic synthesis tool ensure that the gatelevel netlist meets timing, area and power specifications. Afterseveral annotation if the expected output is derived then thefinal implementation is done through FPGA or ASIC. Figure 1depicts the general HDL design flow.IV
 
A
NAYSIS OF
VHDL
AND
V
ERILOG HDL
 A.
 
 Major Capabilities
 
Standard:
 
VHDL
: Has its standardization from IEEEand ANSI [1].
Verilog:
Has its standardization fromIEEE and non-propriety [2].
 
 Language: VHDL:
Language is developed from ADAand Pascal [5].
Verilog:
Language is developed fromC [5].
 
Case sensitive: VHDL:
It
 
is a strongly typedlanguage, and scripts that are not strongly typed, areunable to compile. A strongly typed language likeVHDL does not allow the intermixing, or operationof variables with different clause.
Verilog:
uses weak typing and is case sensitive. It affords the designer asimple language syntax and structure. Because it onlysupports scalar data types, it was possible for thelanguage to perform the correct type conversionsautomatically [9]
 
 Design Methodologies: VHDL:
The languagesupports flexible design methodologies: top-down,bottom-up, or mixed that aid in high-level modelingand it reflects the actual operation of the device beingprogrammed.
Verilog:
Supports both top-down andbottom-up methodologies.
 
 Data types: VHDL:
Complex data types and packagesare very desirable when programming big andcomplex systems that might have a lot of functionalparts.
Verilog:
Simple data types, they are the net andregister data types.
 
General styles of description: VHDL:
There are threegeneral styles of description: structural, dataflow andbehavioral. A design can also be implemented by
Design SpecificationGenerate ModuleInstantiate ModuleCreate Test BenchPerform Behavioral SimulationSynthesize DesignImplement Design
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(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011
mixing all the three styles.
Verilog:
A design can bemodeled in four different styles or in a mixed style.These styles are behavioral, dataflow, gate-level, andswitch-level modeling.
 
Timing Analysis: VHDL:
It supports bothsynchronous and asynchronous timing models.Nominal propagation delays, min-max delays, setupand hold timing, timing constraints, and spikedetection can all be described very naturally in thislanguage [7,8].
Verilog:
The timing verification anddelays like min-max, pin-to-pin delays can beevaluated through analyzer and the systemdirectives.
 
 Range of abstraction levels: VHDL:
It supportsabstraction levels ranging from abstract behavioraldescriptions to very precise gate-level descriptions. Itdoes not support modeling below the transistor level.
Verilog:
A design can be described from switch-level, gate
 – 
level, register- transfer-level (RTL) toalgorithmic-level, including process and queuing-level.
 
Test bench model: VHDL:
Effective testingmethodology can be achieved by developing testbench model to test the MUT ( Model Under Test) atthe behavioral level of abstraction can be reused totest the MUT at the lower levels as well. This featureensures this language is reusable.
Verilog:
Veriloghierarchical referencing (also referred to as Cross-Module-Referencing or XMR or CMR), is a featurethat is extensively used in Verilog test benches. Thisfeature allows simple probing into or monitoring of buried signals without requiring that the signals berouted to the top of design for observation.
 
 Annotations: VHDL:
Generics and attributes areuseful in facilitating the back-annotation of staticinformation such as timing or placement informationand also useful in describing parameterized designs.
Verilog:
 
:
Verilog HDL supports the analysis of critical path delay in a module by specifying throughthe timing parameters in that block. The StandardDelay Format (SDF) in Verilog HDL provides theessential back annotation facility for loading postroute delay calculation.
 
Communication Medium: VHDL-
The language canbe used as a communication medium betweendifferent CAD and CAE tools and also used as anexchange medium between chip vendors and CADtools users.
Verilog-
The Programming LanguageInterface (PLI) is a powerful feature that allows theuser to write custom C code to interact with theinternal data structures of Verilog. Designers cancustomize a Verilog HDL simulator to their needswith the PLI [6].
Analysis
: The two languages have different technicalstrengths which significantly differentiates their market focus.The technical capabilities based solely on ease of use, timingand commercial issues. The following graph (Figure 2)
highlights the language‘s spectrum with respect to the levels
of abstraction. The summary of major capabilities of VHDLand Verilog are listed in Table 1.
Figure 2 Level of AbstractionTable 1 Summary of major capabilities of VHDL and Verilog
 B.
 
Fundamental difference in constructs
VHDL
:
A hardware abstraction of the digital system is calledan entity in VHDL. To describe an entity, VHDL provides fivedifferent types of primary constructs called design unit. Theyare1.
 
Entity declaration2.
 
Architecture body3.
 
Configuration declaration4.
 
Package declaration5.
 
Package body
Capabilities VHDL VerilogStandardization
IEEE and ANSI IEEE and non-propriety
Language
ADA & Pascal C
Case Sensitive
Case-insensitive Case sensitive
Designmethodologies
Top-down, bottom-up,mixedTop-down, bottom-up,mixed
Data Types
Complex Simple
Modeling
Behavioral, data,structuralGate, switch, data,behavioral
Timing analysis
min-max delays, setupand hold timing,min-max delays, setuphold timing and pin-to-pin delay
Abstraction level
Behavioral to gate Behavioral to transistor
Test bench model
Available Available
Annotations
Generics and attributes Standard Delay Format
Communicationmedium
CAD and CAE PLI
129http://sites.google.com/site/ijcsis/ISSN 1947-5500

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