(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011
mixing all the three styles.
A design can bemodeled in four different styles or in a mixed style.These styles are behavioral, dataflow, gate-level, andswitch-level modeling.
Timing Analysis: VHDL:
It supports bothsynchronous and asynchronous timing models.Nominal propagation delays, min-max delays, setupand hold timing, timing constraints, and spikedetection can all be described very naturally in thislanguage [7,8].
The timing verification anddelays like min-max, pin-to-pin delays can beevaluated through analyzer and the systemdirectives.
Range of abstraction levels: VHDL:
It supportsabstraction levels ranging from abstract behavioraldescriptions to very precise gate-level descriptions. Itdoes not support modeling below the transistor level.
A design can be described from switch-level, gate
level, register- transfer-level (RTL) toalgorithmic-level, including process and queuing-level.
Test bench model: VHDL:
Effective testingmethodology can be achieved by developing testbench model to test the MUT ( Model Under Test) atthe behavioral level of abstraction can be reused totest the MUT at the lower levels as well. This featureensures this language is reusable.
Veriloghierarchical referencing (also referred to as Cross-Module-Referencing or XMR or CMR), is a featurethat is extensively used in Verilog test benches. Thisfeature allows simple probing into or monitoring of buried signals without requiring that the signals berouted to the top of design for observation.
Generics and attributes areuseful in facilitating the back-annotation of staticinformation such as timing or placement informationand also useful in describing parameterized designs.
Verilog HDL supports the analysis of critical path delay in a module by specifying throughthe timing parameters in that block. The StandardDelay Format (SDF) in Verilog HDL provides theessential back annotation facility for loading postroute delay calculation.
Communication Medium: VHDL-
The language canbe used as a communication medium betweendifferent CAD and CAE tools and also used as anexchange medium between chip vendors and CADtools users.
The Programming LanguageInterface (PLI) is a powerful feature that allows theuser to write custom C code to interact with theinternal data structures of Verilog. Designers cancustomize a Verilog HDL simulator to their needswith the PLI .
: The two languages have different technicalstrengths which significantly differentiates their market focus.The technical capabilities based solely on ease of use, timingand commercial issues. The following graph (Figure 2)
highlights the language‘s spectrum with respect to the levels
of abstraction. The summary of major capabilities of VHDLand Verilog are listed in Table 1.
Figure 2 Level of AbstractionTable 1 Summary of major capabilities of VHDL and Verilog
Fundamental difference in constructs
A hardware abstraction of the digital system is calledan entity in VHDL. To describe an entity, VHDL provides fivedifferent types of primary constructs called design unit. Theyare1.
Capabilities VHDL VerilogStandardization
IEEE and ANSI IEEE and non-propriety
ADA & Pascal C
Case-insensitive Case sensitive
Top-down, bottom-up,mixedTop-down, bottom-up,mixed
Behavioral, data,structuralGate, switch, data,behavioral
min-max delays, setupand hold timing,min-max delays, setuphold timing and pin-to-pin delay
Behavioral to gate Behavioral to transistor
Test bench model
Generics and attributes Standard Delay Format
CAD and CAE PLI