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ASIP Design Space Exploration: Survey and Issues

ASIP Design Space Exploration: Survey and Issues

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An Application Specific Instruction set Processor (ASIP) is a processor designed for a particular application or for a set of applications. An ASIP exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The main steps involved in ASIP Design Methodology include application analysis, design space exploration, instruction set generation, code synthesis and hardware synthesis. This paper is an attempt to survey the design space exploration of ASIP. Important contributions made by various researchers are also highlighted. A list of explored design space parameters is included in this paper.
An Application Specific Instruction set Processor (ASIP) is a processor designed for a particular application or for a set of applications. An ASIP exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The main steps involved in ASIP Design Methodology include application analysis, design space exploration, instruction set generation, code synthesis and hardware synthesis. This paper is an attempt to survey the design space exploration of ASIP. Important contributions made by various researchers are also highlighted. A list of explored design space parameters is included in this paper.

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(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No.
4
 , 2011
ASIP Design Space Exploration: Survey and Issues
Deepak Gour
Assistant Professor – Dept. of CSESir Padampat Singhania UniversityUdaipur, Indiadeepak.gour@spsu.ac.in 
Dr. M. K. Jain
Assistant Professor – Dept. of CSMohan Lal Sukhadia UniversityUdaipur, Indiamanoj@cse.iitd.ernet.in 
 Abstract
 
An Application Specific Instruction set Processor(ASIP) is a processor designed for a particular application or fora set of applications. An ASIP exploits special characteristics of application(s) to meet the desired performance, cost and powerrequirements. The main steps involved in ASIP DesignMethodology include application analysis, design spaceexploration, instruction set generation, code synthesis andhardware synthesis. This paper is an attempt to survey the designspace exploration of ASIP. Important contributions made byvarious researchers are also highlighted. A list of explored designspace parameters is included in this paper.
 Keywords-
 
 Application Specific Instruction set Processor(ASIP), Design Space Exploration (DSE), Performance estimation,Simulator based approach.
I.
 
I
NTRODUCTION
 An Application Specific Instruction set Processor (ASIP) isa processor designed for a particular application or for a set of applications. An ASIP exploits special characteristics of application(s) to meet the desired performance, cost and powerrequirements. According to Liem et al [1], ASIPs are a balancebetween two extremes: ASICs (Application Specific IntegratedCircuit) and GPP (General Programmable Processors). Sincean ASIC is specially designed for one behavior, it is difficult tomake any changes at a later stage. In such a situation, theASIPs offer the required flexibility at lower cost than GPP.ASIP can be easily used in many embedded systems suchas automotive control, household appliances, cellular phones,avionics etc. GPP are designed for general use. Many times ithappens that specific applications need a certain mix whichdoes not match the GPP resource mix. If we plan to design anASIC to meet the given performance, power and areaconstraints for the given application, deign becomes rigid. Inthe ASIP design, it is important to search for a processorarchitecture that matches target application. To achieve thisgoal, it is essential to estimate design quality of variouscandidate architecture in terms of area, performance, and powerconsumption. Table 1 shows the comparison among GPP,ASIP and ASIC.
GPP ASIP ASICPerformance
Low High Very High
Flexibility
Excellent Good Poor
HW design effort
Nil Large Very Large
SW design effort
Small Large Nil
Power
Large Medium Small
Reuse
Excellent Good Poor
Markets
Very large Relatively large SmallTABLE I. C
OMPARISON AMONG
GPP,
 
ASIP
AND
ASIC
II.
 
RELATED WORK
 This section highlights the major work carried out in theASIP design space explorations. The main contributors areGloria et al [2] who defined some major requirements of thedesign of application specific architectures. Liem et al [1]described the differentiation between the ASIC, ASIP andGPP. MK Jain et al [3, 4, 5, 6, 7] had surveyed ASIP designmethodologies and identified various steps involved in it. Sincethis survey was published in early 2001 and significantcontributions are made by various researchers in due course of time. Sato et al [8] has developed an application programanalyzer which is very useful in the application analysis. Themethodology suggested by Gupta et al [9] takes the applicationas well as the processor architecture as inputs. Using SUIF [10]as an intermediate format a number of application parameter isextracted.Apart from that Swarnalatha Radhakrishnan et al [11]explores the DSE on heterogeneous multiple pipelines. Ascia etal [12] explores the DSE using genetic algorithms onparameterized SOC platforms. Kwon et al [13] explores cachemisses and memory architecture issues. Lilian Gogniat et al[14] explores DSE using special tool called Design Trotter.Kyeong et al [15] explore the DSE on issues related to BusArchitecture. Kim et al [16] explores the DSE on the issues of Area, Critical path delays. Kunzil et al [17] explores the DSEon the issues like # of cache lines, block size and replacementstrategy. Catania et al [18] explores the DSE on the issuesrelated on Register File size (GPR, FPR, PR, CR, BTR) and L1and L2 caches. Pasricha et al [19] explores the DSE on theissues related to the Bus architecture.III.
 
ASIP DESIGN METHODOLOGY
 Gloria et al [2] defined some main requirements of thedesign of application-specific architectures. Important amongthese are as follows:
141http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No.
4
 , 2011
 
Design starts with the application behavior.
 
Evaluate several architectural options.
 
Identify hardware functionalities to speed up theapplication.
 
Introduce hardware resources for frequently usedoperations only if it can be supported duringcompilation.ASIP fits in between these two and provides flexibility atlower cost than general programmable processors. Accordingto MK Jain et al [3, 4, 5, 6, 7] design of ASIP can be typicallydivided in five steps which is shown in Figure 1:
 
Application Analysis
 
Architecture design space Exploration.
 
Instruction-set generation
 
Code synthesis
 
Hardware synthesis
Figure 1. Flow Diagram of ASIP design Methodology
 A.
 
 Application Analysis
ASIP design starts with analysis of application, analysis of test-data and design constraints. An application written in anyhigh level language is analyzed both statically and dynamicallywhich is then stored in some suitable intermediate format,which is then used in the subsequent steps.
 B.
 
 Architecture Design Space Exploration
It involves identifying the broad architectural features of theASIP. First of all, the architectural space to be explored isdefined, keeping in view the parameters extracted duringapplication analysis and the input constraints. Architecture isdefined using some standard Architecture Definition Language(ADL) as EXPRESSION [20] and LISA [21, 22, 23].
C.
 
 Instruction Set Generation
Instruction set is to be generated for that particularapplication and for the architecture selected. This instructionset is used during the code synthesis and hardware synthesissteps.
 D.
 
Code Synthesis
Compiler generator or retargetable code generator is used tosynthesize code for the particular application or for a set of application.
 E.
 
 Hardware Synthesis
In this step the hardware is synthesized using the ASIParchitecture template and instruction set architecture startingfrom a description in VHDL/VERILOG using standard tools.IV.
 
DESIGN SPACE EXPLORATION
 Architecture exploration starts with the application analysis.We need to input the parameters of application analysis alongwith the identified architecture design space to the processblock which is responsible for performance estimation. Thenwe need to do the performance estimation for the inputtedarchitecture along with the search control and then thearchitecture will be selected. Figure 2 explains the procedureof architecture explorer.
Figure 2. Block Diagram of an Architecture Explorer
Performance estimation which drives the design spaceexploration is done by simulator based approach (e.g. Gloria etal [2], Kienhuis et al [24], Imai , Binh et al [25]). Thearchitectural design space is to be explored usually defined interms of a parameterized architectural model.The main focus points are as follows:
 
The parameterized architectural model suggested by allthe researchers includes the number of functional unitsof different types.
142http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No.
4
 , 2011
 
Architectures considered are different researchers alsodiffering in terms of the instruction level parallelismthey support.
 
Most of these approaches consider only flat memory.The most popular approach for ASIP design spaceexploration is simulator based approach. In the simulator basedapproach, a simulation model of architecture based on theselected features is generated and the application is simulatedon this model to compute the performance. Figure 3 explainsthe functioning of simulator based approach.
Figure 3. Architecture exploring using simulator based approach
V.
 
PARAMETERS EXPLORED IN DESIGN SPACE EXPLORATION
 In the recent past the major work carried out in DesignSpace Exploration is by using Simulator based approach. Themajor contributions are as follows:Swarnalatha Radhakrishnan et al [11] explores the DSE onheterogeneous multiple pipelines. She proposed ApplicationSpeci_c Instruction Set Processors with heterogeneous multiplepipelines to efficiently exploit the available parallelism atinstruction level. We have developed a design system based onthe Thumb processor architecture. Given an applicationspecified in C language, the design system can generate aprocessor with a number of pipelines specifically suitable to theapplication, and the parallel code associated with the processor.Each pipeline in such a processor is customized, andimplements its own special instruction set so that theinstructions can be executed in parallel with low hardwareoverhead.Ascia, Vincenz Catania, Palesi et al [12] explores the DSEusing genetic algorithms on parameterized SOC platforms. Thebasic idea is to avoid designing a chip from scratch. Theyproposed an approach based on genetic algorithms forexploring the design space of parameterized system-on-a-chip(SOC) platforms. The strategy focuses on exploration of thearchitectural parameters of the processor, memory subsystemand bus, making up the hardware kernel of a parameterizedSOC platform for the design of embedded systems with strictpower consumption and performance constraints. The approachhas been validated on two different parameterizedarchitectures: one based on a RISC processor and anotherbased on a parameterized very long instruction wordarchitecture.Kwon, Lee, Kim, Ha et al [13] explores cache misses andmemory arschitecture issues using Y-Chart approach to DSE.Y chart consists of two loops as 1) Co-synthesis loop forcomponent selection and mapping of the function blocks to theprocessing components and 2) Communication DSE loop forcommunication architecture optimization.Lilian Gogniat, Phillipe et al [14] explores DSE usingspecial tool called Design Trotter. This tool allow for theexploration of their design space to choose the best architecturecharacteristics. They proposed an original approach based on ahigh-level representation of the application and on ahierarchical functional model for the architecture. Thisapproach targets fine-grain, coarse-grain, and heterogeneousarchitectures.Kyeong, Mooney et al [15] explore the DSE on issuesrelated to Bus Architecture where they propose Bus Synthesistool to generate the five different bus systems. This paperpresents a methodology to generate a custom bus system for amultiprocessor System-on-a-Chip (SoC). Our bus synthesistool (BusSyn) uses this methodology to generate five differentbus systems as examples: Bi-FIFO Bus Architecture (BFBA),Global Bus Architecture Version I (GBAVI), Global BusArchitecture Version III (GBAVIII), Hybrid bus architecture(Hybrid) and Split Bus Architecture (SplitBA). They verifiedand evaluate the performance of each bus system in the contextof two applications: an Orthogonal Frequency DivisionMultiplexing (OFDM) wireless transmitter and an MPEG2decoder. This methodology gives the designer a great benefit infast design space exploration of bus architectures across avariety of performance impacting factors such as bus types,processor types and software programming style.Kim, Keimh, Choi et al [16] explores the DSE on the issuesof Area, Critical path delays. The optimization is based onpipelining and sharing of functional resources in the PE of thearray. They proposed efficient design space exploration flowwith two optimization techniques. The optimization is based onpipelining and sharing of functional resources in the processingelements of the array. For fast architecture exploration,optimization techniques are applied to SystemC model. Theyestimated entire performance at early stage by transaction levelsimulation and this feature enables early detection of optimalarchitecture specification. With proposed design spaceexploration, one can effectively reduced the hardware costwithout any performance degradation for a specific applicationdomain.Kunzil, Thiele et al [17] explores the DSE on the issues like# of cache lines, block size and replacement strategy. A genericapproach is described based on multi-objective decisionmaking, black-box optimization and randomized searchstrategies. The interface between problem-specific and genericparts of the exploration framework is made explicit by definingan interface called PISA. This specification andimplementation interface, and the availability of a wide rangeof randomized multi-objective search methods, makes theproposed framework accessible to a wide range of explorationproblems. It resolves the problem that existing optimizationmethods cannot be coupled easily to the problem specific partof a design exploration tool.Ascia, Catania et al [18] explores the DSE on the issuesrelated on Register File size (GPR, FPR, PR, CR, BTR) and L1
143http://sites.google.com/site/ijcsis/ISSN 1947-5500

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