Implementation of Direct Processor Access inTransient Nodes
P. S. BALAMURUGAN, K.THANUSHKODI,
Research Scholar , Director ,
Anna University of Technology, Akshaya College of Engineering and Technology,Coimbatore . Coimbatore.
Abstract-
Wireless sensor networks faces a number of challenges; a wireless sensor network which includes a numberof sensor nodes must provide reliability and fault toleranceagainst a number of odds such as scalability, hardware,environmental conditions, power and energy factors. In thispaper, we address these two issues of Reliability and FaultTolerance using mirror nodes. We demonstrate that increasedreliability can be achieved by using mirror nodes and the costscould be maintained by implementing the Direct ProcessorAccess(DPA). Experimental results on the benchmarks data setshow that our proposed system based on Direct ProcessorAccess outperforms the other well-known methods such as theDistributed Deviation Detection, Distributed anomalydetection, Intrusion detection for routing attacks, Statistical enroute filtering and Abnormal Relationship Tests(ART). Theimprovement in performance using DPA is very high,particularly, for the graphical and network processes (6.8percent improvement). Statistical Tests also demonstratehigher fault tolerance and improvement in performance forour method. Finally, we show that our system is robust and isable to handle faulty sensor nodes without compromisingperformance.
Keywords -
Wireless Sensor Networks,;Faulty Sensor Nodes;Fault Tolerance; Direct Processor Access ;Mirror Nodes
I. INTRODUCTIONA wireless sensor network (WSN) is a collection of nodesorganized in a network where each node consists of one ormore microcontrollers, CPU’s or DSP chips, a memory anda RF transceiver, a power source such as battery. It alsoaccommodates various sensors and actuators. The nodescommunicate without wire (wireless) and often organizeitself after being deployed in an ad hoc fashion . Theintrinsic properties of individual sensor nodes poseadditional challenges to the communication protocols interms of energy consumption.The reliability or fault tolerance is yet anotherissue. Some sensor nodes may fail or be blocked due to lack of power, physical damage or environmental interference.The failure of sensor nodes should not affect the overall task of the sensor network.
A. Challenges of Wireless Sensor Networks
In monitoring sensor networks, data coming from variousstreams of the sensor nodes have to be examineddynamically and combined into normal patterns in order todetect potential anomalies. Due to the requirement for thesupport of mission critical applications in many cases, thesensors must possess mechanisms for securingcommunications and for validating the collected data.Several attack scenarios that exploit the weaknesses of WSNs has been identified and the scale of deployments of WSNs requires careful decisions and tradeoffs amongvarious security measures. These issues are taken intoconsideration and mechanisms to achieve a higher level of security and reliability has been proposed in these networks.II. WIRELESS SENSOR NETWORK WITH MIRRORNODESIn this investigation, we assign a mirror node for eachmaster node. At a time only a single node will be activated,either master node or mirror node. The mirror node will bein active state only in the absence of the master node.Whenever master node is identified as faulty node, theprimary node will activate the mirror node and isolate themaster node from the sensor network. This process helps toimprove the availability of the sensor networks duringthreats and disaster and its performance is shown in Fig 1.
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011162http://sites.google.com/site/ijcsis/ISSN 1947-5500
Data Transmission rate in
sensor network withmirror nodes (MB/ s)
Data Transmission rate in
sensor network withoutmirror nodes(MB/s)
0.2
0.1
0.4
0.22
0.45
0.33
0.52
0.34
0.56
0.41
0.59
0.42
0.61
0.43
0.67
0.46
0.69
0.51
0.74
0.52
0.78
0.54
Data Transmission rate in sensor
network with Asynchronousmirror (MB/s)
Data Transmission rate in
sensor network without Mirrornodes (MB/ s)
0.190.1
0.350.22
0.4120.33
0.4520.34
0.5160.41
0.580.42
0.590.43
0.640.46
0.6560.51
0.7140.52
0.7280.54
0.7810.56
TABLE 1: PERFORMANCE OF SENSOR NETWORK WITH MIRRORNODES
If the cost of the network is more expensive than deployingtraditional sensors, then the sensor network is not cost justified. we have formulated two approaches for allocatingmonitor node for a cluster. Clustering can be structuredasymmetrically or symmetrically. In asymmetric clustering,one machine is in non dedicated mode while the other isacquiring real time data. The non dedicated host doesnothing but simply monitors the remaining nodes in thecluster. If any node fails, then the non dedicated hostbecomes the active node. In the second approach, two ormore hosts are monitoring each other. If any node in the co-operating system fails, then the monitoring nodes share theworkload of faulty nodes among them. These approachesare useful where maximum reliability and availability arerequired and its performance is shown in fig 3.
TABLE 2: PERFORMANCE OF SENSOR NETWORK WITHASYNCHRONOUS MIRROR NODES
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1s
3s
5s
7s
9s
11s
Series1
Series2
Figure 1:Performance of sensor network with mirror nodes
In the previous investigation, the availability of the sensornetworks was increased to the optimum level. But thesensor networks consist of a large number of sensor nodesand implanting a mirror node for each individual sensornode will increase the overall cost of the networks.
0.90.80.70.60.50.40.30.20.101 s 3 s 5 s 7 s 9 s 11 sSeries1Series2
Figure 2: Structure of Sensor node with asynchronous mirror nodeFigure 3: Performance graph for asymmetric mirror nodes
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011163http://sites.google.com/site/ijcsis/ISSN 1947-5500
Time delay for a sensor
network without mirror insensor network (ns)
Time delay for a sensor
network with asynchronousmirror in sensor network (ns)
0.2
0.1
0.31
0.23
0.42
0.28
0.46
0.31
0.51
0.344
0.62
0.38
0.74
0.51
0.89
0.64
0.916
0.7
TABLE 3: COMPARISON OF TIME DELAY FOR A SENSORNETWORK WITH ASYNCHRONOUS MIRROR NODE ANDWITHOUT MIRROR NODE
processor can access the data and codes easily, by searchingin the specified memory location. By this procedure thevalue n will not represent the total cache memory space butit will represent only the value of an array. When a programneeds more memory space than the allotted memory byusing artificial intelligence we can combine the memory andutilize it to execute the program. The process of combiningmemory can be done by calculating the frequently usedprogram or FIFO method. This method is highly applicablewhen we need to run a program which needs memory spaceless than n/11 in a high RAM capacity machine. In thismethodology the work of the processor is simplified byallowing it to search in the allotted array. Array MethodologyCo – Processor (DSP)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1 ns
3ns
5 ns
7ns
9
ns
Series1
Series2
CD DriveProcessor unit(Multi core Processor)Array Methodology(FPGA)
Figre 4: Time delay for a sensor network having mirror node and withoutmirror node
From these comparisons we could conclude thatintroducing mirror nodes will obviously improve theperformance of sensor networks. Hence sensor networkswith mirror nodes can be implemented in real time systemswhere time constraints are strictly followed and cost factoris not an issue.III. DPA in Sensor Network To increase the accessing speed and to attain an efficientmemory access, a new methodology is employed in theproposed system. The methodology is termed as ArrayMethodology. By this methodology the processor willinteract with the RAM device in an array fashion by whichthe RAM will be divided into arrays and each array will beallotted for a default program to be utilized. Thus the
Figure 5: Block Diagram of Array methodology Based Co - ProcessorDesign
Another important concern that influences the processorperformance is the heat sink designed for the IC and thedesign has to be chosen between its size and performance.The impact of CMOS technologies on substrate and metalline temperatures have resulted in improved reliability andbetter performance of the devices and interconnections. 74% of processor failures are due to thermal factors and highpower sources such as power dissipation, temperaturerelation, a method for full chip temperature calculation andimplications on the design of high performance low powerVLSI circuits. By spacing the memory in an array manner,the cache port’s accessibility could be improved. This canbe known from the percentage of hit ratio tabulated for thedifferent programs.
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 4, April 2011164http://sites.google.com/site/ijcsis/ISSN 1947-5500
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Implementation of Direct Processor Access in Transient Faulty Nodes
Wireless sensor networks faces a number of challenges; a wireless sensor network which includes a number of sensor nodes must provide reliability and fault tolerance against a number of odds such as scalability, hardware, environmental conditions,…
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