ixedmsignal Circuit Simulation
ith Behavioral Modeling Cap
Joseph T. Smith and Harold K. Brown
Florida Institute of Technology
150 W. Universit Boulevard
Melbourne, F l 32901
(407) 768-8000 ext. 7180
email: jts@ee.fit.edu
Abstract
In this paper, the development of a mixed-signal circuit
simulation system with behavioral modeling capability is
discussed. In this context, mixed-signalsimulation refers to
the simulationof circuits and systems containingboth analog
and digital cells excited with signals of either an analog or
digital nature. The backgroundinformation regardingcircuit
simulation is given along with a discussion of device and
system modelingfor analog and digital cells. In addition, the
numericalmethods and programmingtechniques along with
how these relate to the internal data structure are analyzed.
Finally, the scenarios used for testing the simulator are
discussedand the resultscomparedto results obtainedfrom
the SPICE simulator using device based models.
The development of this simulation system has provided a
seamless methodfor developing behavioral models given a
cell which has been well characterized. These behavioral
models are developedutilizingobject-orientedprogramming
techniques and are capable of providing highly accurate
results. Behavioral cells, once developed, can then be
simulated with signals and cells of an analog or digital nature
to provide significant improvements in simulation times of
large systems.
1 Introduction
Overthelastthirtyyears, the sizeand complexityof electronic
circuits has grown at a remarkable rate and thus has placed
great demands on the developers of simulation tools. For
example, it is not unusual to find systems such as micro-
processors that exhibittransistorcounts well into the millions.
In order to design such a system, it is necessary for teams
of engineers to work together on the design, segmenting it
into sub-moduleswhich may be inherently analog or digital
and developing these submodules separately utilizing tools
which allow for mixed-signal simulation. Even with the
segmentation of these large designs, the overall complexity
and sheer size of a system may overcome available com-
puting. resources. Thus, the designers must come up with
ehaworal models which are computationallyefficient but do
not sacrifice a great deal of accuracy. For this reason, it is
verydesirableto have a simulationtool which is very modular
by design which can facilitate the interconnection of very
large subsystems and/or macro-behavioral models which
describe these subsystems in a seamless manner. It is also
desirable for such a system to have the capability of being
parallelized so that the computations associated with large
simulations could be distributed over a number of machines.
The purpose of this researchwas to developthe groundwork
for a new circuit simulation system which while supporting
the SPICE netlist format, will contain added functionality,
improvedmodularity,parallel capability, and the capabilityto
implement macro-behavioral models in a way which is
transparent to the user.
580
2 Simulation Fundamentals
The basic understandingof certain fundamentals regarding
the internal workings of a simulator such as the simulation
system developed during this research is helpful for the
comprehensionof the results that have been achieved. For
this reason, a brief but concisesummary of the key numerical
and modelingtechniques is given in this section.
Modified Nodal Analysis
As it's name implies, modified nodal analysis is a variation
of the method of nodal analysis. This method is based on
Kirchoff's current law which states that the algebraic sum of
all currents entering a node is equal to zero.
In order to describe the current flow in a system, circuit
equations of the following form must be composedfor every
node:
G,,V,+G,,V,. ..+G,,V"=I, 2.1
G,, V , + G,V,.. .+ G,V, =I, 2.2
G , V , + G,V,. ..+ G,V, = 1. 2.3
In matrix notation, these equations are expressedas follows:
G*V=I 2.4
where G -epresentsthe nx nadmittancematrix whosevalues
are known, V is the voltage vector of dimension n whose
values will be solved for, and I is the current vector of
dimension n whose values are known.[l]
Where modified nodal analysis deviates from the method of
nodal analysis is.how the method deals with the infinite
admittance associated with an ideal voltage source. For
each voltage source in a given circuit, a new equation is
formed (and thus a row and column is added to the MNA
matrix). The new equationthat is placed in the matrix is now
solved for the current instead of the voltage.
Analog System Modeling
The modelin of analog elements such as resistors,
capacitors,inluctors, etc. is achieved in one of two ways. In
the case of linear elements such as resistors,the contribution
of the element to the MNA matrix (or the stamp) is simply
placed into the matrix at the appropriate time during the
simulation. For non-linear elements such as capacitors,
inductors, and diodes, a companion model must be formu-
lated which usually consists of dependent and/or indepen-
dent sources and admittances whose values are determined
utilizing numericaltechniques such as numerical inte ration
and Newton-Raphsoniteration. The contributions ogthese
companion models are then placed into the MNA matrix at
each timestep.[l-5, 7-9, 111
Digital System Modeling
As in the case of analog system modeling, the modelin of
digital elements can be achieved in one of two ways. 8ne
way that this can be done is to model the digital element at
thedevice ortransistor level. However, in large systems, the
modeling of digital elements at the device level becomes
compute intensive and can someltimes overcome ones
compute resources. A more acceptable solution is to
represent well characterized system:; with macro-behavioral
models which reduce the computational burden while pro-
viding highly accurate results. This simulation system uses
the exponential running averagle technique in the
implementationof these macro-behavioral models.[6, I O ]
Exponential Running Average Technique
It is common in the realm of digital system design for one to
observe in the response of digital systems a rounding of
square (or nearly square) wave edges which becomes more
and more pronounced as the excitation frequencies
increase. In the modeling of this wave edge rounding, it can
be assumed that the observed responsecorresponds to that
of a first-order RC low pass filter.[l3:1
R which will define unique element types. Within these derived
-
+
7 and the member functions that aid in the implementation of
-L
I +
vin "out
cL
T functions are defined as follows: "A virtual function is a
0 instance invokedis determined by the class type of the actual
Figure 2.34 First Order RC lLew Pass Filter
When a LaplaceTransform is erformedon this circuit, it can
be found that the transfer knction of the circuit in the
s-domain is:
2.5
F ( s )=- 1 1
1 +sRC - 1+s,u
where 'c = RC.
The equation given above expresses the transfer function of
thecircuitin acontinuous sense. However,forthe calculation
of this responseonacomputerfosthepurposesofsimulation,
it would be desirable to obtain a discrete expression. A
discrete expression for this response can be obtained b
performing a z-transformon the circuit transfer function.[4{
Y" + 1 = (1- aY, + U,+l 2.6
lnthis expression,I(,,+, correspondsto the input beingapplied
at the present timestep and Y, and Y,+, are the outputs of
the circuit at the previous and present timestep respectively.
The t!me constant of the circuit is related to the previous
equation by the following expression.
2.7
This method has proved useful in the development of the
behavioral models of digital elements implemented in this
simulation system due to it's computational simplicity.
In the development of this software, object oriented pro-
gramming techniques were utilized in order to achieve the
modular data structure necessary for a successful circuit
simulation system. The primary techniques used were
inheritance and polymorphism (utilizing virtual functions).
Every element of a circuit has certain attributes associated
with it. Some of these attributes are unique to a particular
element but others can be thought of as being generic; t
term generic meaning that this particular attribute can
defined in the same manner for any given element. This
particular property of circuit elements can be used to define
a class structure that lends itself to the problemat hand. The
way this is done is to design a base class which will be
inherited by all subsequently derived classes. Within the
base class, all of the cell properties and member functions
that will act as the interfaceto these cell propertieswhich are
commonto all of the different cell types will be defined. These
common pro erties will include such things as the name of
the device, tge device t pe, the number of internal nodes,
and the number of MNA(matrix contributions to mention a
few. This base class will then be inherited by other classes
classes, all of the properties that make an element unique
these properties will be defined.
The use of virtual functions was essential for providing the
type of generality necessary for developing a simulation
capable of being expanded in a logical manner. Virtual
special member function invokedthrough a publicbase class
reference or pointer; it is bound dynamically at run time. The
object addressed by the pointer or reference. Resolutionof
a virtual function is transparent to the user."[l2] What this
means is that the simulator does not have knowledge of and
is not concerned with what type of cell it is dealing with. It
simply knows that it has certain functions that it must erform
for each cell. These functions are uniquely defined L r each
cell type and the resolution of these function calls is deter-
mined at simulation time.
4 Conclusion
The systemdevelopedduringthis researchwas tested under
a select number of test conditions using built-in cells utilizing
behavioralmodels and the results comparedwith the results
of SPICE simulations of identical circuits using transis-
tor-level models of the same elements. There was also a
test run which compared the performance of the simulation
system developed during this research using device-based
models and behavioral models. In the testing phase, the
attempt was made to demonstrate the increase in compu-
tational speed realized by the exclusive use of behavioral
models in the circuits being simulated. Also, the ability of the
simulationsystemto deal with systems which containsignals
of an analog nature interacting with digital cells and non-
linear elements was examined. Convergence issues
encountered in this testing phase were then evaluated.
Simulation Test Cases
initial testing of this simulation system involved the testing
of digital elements without the presence of non-linear ele-
ments. The NAND gate was tested by applying piecewise
linear inputs whose values generated outputs verifying the
losic function performed by a single gate. The diagram of
this test circuit is shown in Figure 4.1,
 I
0 PWL

Qpm
Figure 4.1 Simulator Test Case Circuit #1
The next test case that was evaluated was circuit in which a
number of NAND gates were connected together into a
flip-flop configuration. This was done in order to evaluate
the performance of these models when more than one gate
is simu!ated in a system. The diagram of this test circuit is
shown in Figure 4.2.
-r 1 -
c'wkY5v
LCL, -
Flgure 4.2 Simulator Test Case Circuit #2
The third test case that was evaluated involved the inter-
connection of an RLC network with the flip-flop circuit
pictured in Figure 4.2. The purpose of this test case was to
establish the ability of the behavioral NAND gate model to
deal with ill behaved input signals yielding accurate resutts
in a timely fashion. A schematic of this test circuit is shown
in Figure 4.3.
i
-
I
U
I
A-
Figure 4.4 Simulator Test Case Circuit ##4
In the test case pictured in Figure 4.4, it was found that the
use of behavioral models decreased simulation times with
respect to identical simulations run with a device-based
model of the AND gate. The ratio of the two simulationtimes
shows an improvement of 6.36X.
The final circuit configuration that was tested involved the
interconnection of an RLC network being driven by a
piecewiselinear source, and a Dflip-flopcomprised of NAND
gates with clamping diodes connected to one of the inputs.
This was done to evaluate whether there are any conver-
gence issues associated with signals of an analog nature
driving non-linear elements connected to digital elements. A
schematic of this circuit is shown in Figure 4.5 and the
inputloutput voltages of the circuit are displayed in Figure
4.6. The simulationtimewas not addressedforthistestcase.
"-
Q
D
-
Q

Figure 4.5 Simulator Test Case Circuit #5

1f , , , , , , , , I ,

Figure 4.3 Simulator Test Case Circuit #3

Although the comparison of simulation times using behav-
ioral models compared to simulations using device based
models run on SPICE does give an indication of the speed
enhancements derived from using behavioral models, the
level of enhancement that is observed is somewhat con-
servative. This is due to the sparse matrix storage mecha-
nism used in SPICE and the matrix solving routines which
are optimized to operate solely on the non-zero elements of
the matrix (Typically about 2% of the MNA matrix). This
sparse-matrix storage mechanism and corresponding sob-
ing routines were not included in this simulation system. For
this reason the fourth test case involved the comparison of
simulation times of behavioral and device-based (diode 1
0 le Q2l
cQl IcOl 4c-01 %Ul &Ol 1Cm Scm 9r-07 ISM
logic) AND gate implementations run solely under the fimc ( U s d )
simulation system developed during this research. This
simulation test case was designed to more accurately Figure 4.6 Test Case #5 Input and Output Voltages
represent the speed enhancement achieved when behav-
ioral models are used by providing equal testing conditions.
Comparison to SPICE Simulations Using Device-
Based Models
After evaluating the performance of the circuits given in
Figures 4.1,4.2,and 4.3,. SPICE rsi.mulations of the same
circuitswere performedusing a tranlsistor-level model forthe
NAND gate. It was determined from the results of these
simulations that this simulation system performed very
favorably in comparison to the same circuits simulated in
SPICE on the same computing platliorm. However, it should
be noted that speed improvements shown are not as large
as they should be due to the absence of a sparse matrix
storage mechanism and LU decomposition(matrix solution)
algorithms optimized for that storage in this simulation
system. These results are summarized in Table 4.1.

Beh. Mod. Time

Figure 4.7 Test Case #2 Input and Output Voltages

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0 le07 h-07 3007 4F-07 Se47 6-07 7-01 &-07 BO1 le06
T- (=&I)

Flgure 4.6 Test Case #1 Input and Output Voltages

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