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Article history: In this paper, a new topology of cascaded multilevel inverter using a reduced number of switches, insu-
Received 29 November 2008 lated gate driver circuits and voltage standing on switches is proposed. The proposed topology results in
Accepted 29 June 2009 reduction of installation area and cost and has simplicity of control system. This structure consists of ser-
Available online 28 July 2009
ies connected sub-multilevel inverters blocks. Three algorithms for determination of magnitudes of dc
voltage sources have been presented, too. Validity of the analysis has been proved by simulation and
Keywords: experimental results.
Multilevel inverter
Crown Copyright Ó 2009 Published by Elsevier Ltd. All rights reserved.
Cascaded multilevel inverter
Sub-multilevel inverter
Full-bridge
H-bridge
0196-8904/$ - see front matter Crown Copyright Ó 2009 Published by Elsevier Ltd. All rights reserved.
doi:10.1016/j.enconman.2009.06.032
2762 E. Babaei, S.H. Hosseini / Energy Conversion and Management 50 (2009) 2761–2767
S1,1 S 3,1
+ S1 S2
+ Vdc vo
+
V1 vo ,1
−
S 4,1 S 2,1
Fig. 2. Suggested basic unit for a sub-multilevel inverter.
Table 1
S1, 2 S 3, 2 Values of vo for states of switches S1 and S2.
+ State Switches states vo
+ vo , 2
V2 S1 S2
− vo
S 4, 2 S 2, 2 1 On Off Vdc
2 Off On 0
vo
V1 + V2 + V3 + V4 V1 + +
V1 + V2 + V3 S1 S2 vo ,1
V1 + V2 −
V1 T1 D T3 D
1 3
S1′ S3′
0 T 2T t V2 + +
S3 S4 vo , 2
+ vL −
Fig. 4. Typical output waveform of 5-level.
− v
o
iL
waveform of the proposed multilevel inverter. As this figure shows,
the output voltage for all times has zero or positive value.
In the following, we propose three different methods for deter- T4 T2 D
D4 2
mination of magnitudes of dc voltage sources which are used in the
proposed multilevel inverter. It is worth noting that by all pro- Vn + S 2 n−1 + S 4′ S 2′
posed methods, every number of output voltage steps (even and
S 2n vo ,n
odd) can be produced. −
3.1. First method Fig. 5. The proposed structure for generating both of the positive and negative
output voltages.
If all dc voltage sources in Fig. 3 equal to Vdc, the inverter is then
known as symmetric multilevel inverter. The number of maximum
figure, the full-bridge topology added to the output terminals of
output voltage steps of the n series basic units can be evaluated by:
the circuit shown in Fig. 3. The direction of load current and volt-
Nstep ¼ n þ 1 ð8Þ age are as shown in Fig. 5. It is clear that both switches S01 and S04 (or
S02 and S03 ) can not be on simultaneously because a short circuit
The reason for using the term ‘‘maximum” is that it is possible
across the voltage vo would be produced. There are four defined
to have an equal value for vo over different states of the switches.
switch states as shown in Table 3. Fig. 6 shows a 9-level typical
The maximum output voltage is given by:
output waveform of the proposed multilevel inverter. The switches
V o;max ¼ n V dc ð9Þ S01 and S02 are fired together and conduct for 0 < t < T. At t = T, the
switches S01 and S02 are turned off and the switches S03 and S04 are
turned on. Thus S03 and S04 conduct for the duration T < t < 2T. For
3.2. Second method
this duration, the direction of vL is opposite to vo as shown in
The second method for determination of the magnitudes of dc
voltage sources is in binary fashion which gives an exponential
increasing in the number of the overall output levels. For n series Table 3
basic units, with dc voltage levels varying in binary fashion, the Switches states for a full-bridge.
number of maximum output voltage steps and maximum output State Switches states vL Components conducting
voltage are calculated by Eqs. (10) and (6), respectively.
S01 S02 S03 S04
Nstep ¼ 2n ð10Þ 1 On On Off Off vo T1 and T2 if iL > 0
D1 and D2 if iL < 0
2 Off Off On On vo D3 and D4 if iL > 0
3.3. Third method T3 and T4 if iL < 0
3 On Off On Off 0 T1 and D3 if iL > 0
In the third method, the dc voltage sources in the proposed D1 and T3 if iL < 0
multilevel inverters are suggested to be chosen according to the 4 Off On Off On 0 D4 and T2 if iL > 0
T4 and D2 if iL < 0
following equations:
V 1 ¼ V dc ð11Þ
V j ¼ 2V dc for j ¼ 2; 3; 4; . . . ; n ð12Þ
The number of maximum output voltage steps can be deter-
mined by the following equation: vL
Nstep ¼ 2n ð13Þ
V1 + V2 + V3 + V4
V1 + V2 + V3
The maximum output voltage of this n cascaded multilevel in- V1 + V2
verter is:
V1
V o;max ¼ ð2n 1ÞV dc ð14Þ T 2T
0
t
−V1
4. Extended structure −(V1 + V2 )
−(V1 + V2 + V3 )
The multilevel proposed in Fig. 3, only can generate the positive
−(V1 + V2 + V3 + V4 )
output voltages. For generating both of the positive and negative
output voltages, the structure shown in Fig. 5 is proposed. In this Fig. 6. Typical output waveform of 9-level.
2764 E. Babaei, S.H. Hosseini / Energy Conversion and Management 50 (2009) 2761–2767
Fig. 6 and the negative half of output waveform is obtained. Diodes Table 5
D1–D4 act as freewheeling operation. Comparison of power component requirements for suggested multilevel inverter.
In the topology shown in Fig. 5, the number of maximum output First method Second Third method
voltage steps for three methods mentioned in Section 3 is given by method
the following equations, respectively: Maximum output voltage V dc
N step 1 N
V dc step2
1
V dc
N step 1
2 2
First method:
Number of switches, IGBTs and Nstep + 3 2 ln½2ðNstep þ1Þ N step þ9
ln 2 2
Nstep ¼ 2n þ 1 ð15Þ gate drivers
Number of capacitors N step 1 lnðN step þ1Þ
1
N step þ1
2 ln 2 4
Second method: Variety of magnitudes of dc 1 lnðN step þ1Þ 2
ln 2
1
nþ1 voltage sources
Nstep ¼ 2 1 ð16Þ Standing voltage on S1–S2n Vdc(Nstep 1) Vdc(Nstep 1) Vdc(Nstep 1)
Standing voltage on S01 —S04 2Vdc(Nstep 1) 2Vdc(Nstep 1) 2Vdc(Nstep 1)
Third method:
Standing voltage on all of the 3Vdc(Nstep 1) 3Vdc(Nstep 1) 3Vdc(Nstep 1)
Nstep ¼ 4n 1 ð17Þ switches
Table 4
150
Comparison of power component requirements among conventional cascaded
multilevel inverters. Conventional Suggested
Symmetrical Symmetrical 100
Binary Trinary
50
Maximum output voltage V dc
N step 1 N
V dc step2
1 N
V dc step2
1
2
h i
Number of switches, IGBTs 2(Nstep 1) 4
lnðN step þ1Þ
1
4 ln N step
ln 2 ln 3
and gate drivers 0
Number of capacitors N step 1 lnðN step þ1Þ
1
ln N step 0 25 50 75 100
2 ln 2 ln 3
Variety of magnitudes of dc 1 lnðN step þ1Þ ln N step No. of voltage steps
ln 2
1 ln 3
voltage sources
Standing voltage 2Vdc(Nstep 1) 2Vdc(Nstep 1) 2Vdc(Nstep 1) Fig. 8. Comparison of the standing voltage on switches S1–S2n to realize Nstep
voltages in the suggested structure and conventional cascaded inverter.
E. Babaei, S.H. Hosseini / Energy Conversion and Management 50 (2009) 2761–2767 2765
150
6. Simulation and experimental results
Trinary
100 To examine the performance of the proposed multilevel inver-
Binary ter in the generation of a desired output voltage waveform, a pro-
50 totype is simulated and implemented based on the proposed
topology according to that one shown in Fig. 11. The PSCAD soft-
ware has been used for simulation. The multilevel shown in
0
0 25 50 75 100 Fig. 11 is a 11-level multilevel inverter and can generate staircase
No. of voltage steps waveform with maximum 100 V on output. The load is a series R–L
(a) Conventional cascaded inverter with magnitudes 70 X and 55 mH, respectively.
There are several modulation strategies for multilevel inverters
[12,24–28]. In this work, the fundamental frequency switching
100 technique has been used. The benefit of the fundamental frequency
switching method is its low switching frequency compared to the
No. of switches
First method other control methods [25]. Table 6 shows the ON switches look-
Third method
up table and Fig. 12 shows the control block diagram of the inver-
ter. Note that there are different switching patterns for producing
50
the zero level, and in Table 6 only one of them is shown. The main
Second method
0 + +
0 25 50 75 100 + S1 S2
No. of voltage steps 20V vo1
−
(b) Suggested structure S1′ S3′
Fig. 9. Comparison of the required number of switches to realize Nstep voltages. +
+ S3 S4
20V vo 2
−
Variety of magnitudes of sources
6
+ + vL −
Binary
+ S5 S6 vo 3
20V vo
− iL
3
Symmetrical Trinary +
+ S7 S8 vo 4
20V
1
− S 4′ S 2′
0
0 25 50 75 100
+
No. of voltage steps + S9 S10 v o5
(a) Conventional cascaded inverter 20V
− −
Variety of magnitudes of sources
Single − phase IL
iL 2.0
11 − level +
vL
Decision multilevel converter 1.0
Setting −
Unit ( Fig.11)
0.0
Levels Gate Signals
Fig. 12. Control block diagram. 0.0000 0.0100 0.0200 0.0300 0.0400 0.0500
Vo1
30
20
10
0
Vo2
30
20
10
0
Vo3
30
20
10
20
VL
120 10
80 0
40 Vo5
30
0
20
-40
10
-80
0
Fig. 14. Simulated output voltage (vL). Fig. 16. Output voltage of units.
E. Babaei, S.H. Hosseini / Energy Conversion and Management 50 (2009) 2761–2767 2767