HIGH YIELD DENSE ARRAY OF VERY-HIGH-ASPECT-RATIO
MICRO METAL POSTS BY PHOTO-ELECTROCHEMICAL ETCHING
OF SILICON AND ELECTROPLATING WITH VACUUM DEGASSING
Guangyi Sun1, 2, Janet Hur1, Xin Zhao2 and Chang-Jin “CJ” Kim1
1
University of California, Los Angeles (UCLA), California, U.S.A.
2
Nankai University, Tianjin, China
ABSTRACT
A high yield fabrication of a dense array of
very-high-aspect-ratio (VHAR) freestanding metal
posts over a large area is presented. The fabrication is
based on photo-electrochemical etching of silicon and
bottom-up electroplating of the metal. By using
various new techniques, most notably
degassing-assisted electroplating, freestanding nickel
posts with aspect ratio and height up to 85:1 and 425
μm, respectively, are realized. While the increase in
the aspect ratio of the posts may appear more
revealing, the dramatic improvement in yield and
uniformity is often more important for applications.
The report is over our entire processing area (3 cm2),
unlike most others in the literature (1 mm2 - 1 cm2).
INTRODUCTION
The fabrication of high-aspect-ratio metal structures
is of central interest for many applications of
microelectromechanical systems (MEMS). For
example, an array of metals was formed through a
silicon wafer in a high aspect ratio (HAR) so that
such through-silicon-metal-vias would interconnect
multiple circuit layers for three-dimensional (3-D)
integrated circuit (IC) [1], which offers significant
improvements over two-dimensional (2-D) IC on
response time, integration density, and reliability. For
another example, a dense array of HAR metal posts
was fabricated to serve as the 3-D electrodes [2] for
3-D batteries, which produce more energy and power
than what traditional 2-D planar electrodes do on a
given footprint area while sustaining high discharge
rates [3]. Both the examples use etching to form an
array of through-holes in silicon wafer and fill the
holes with a metal by electroplating. The latter
example (i.e., 3-D battery) further removes the silicon
to release the metal into freestanding 3D electrodes.
To fabricate HAR metal structures as demanding as
in the above examples, several key technological
challenges must be addressed. One is to how to form
very deep (e.g., through-wafer) holes that are only a
few microns in diameter and in spacing. Another is
how to achieve void-free electroplating to fill such
978-1-4244-5763-2/10/$26.00 ©2010 IEEE
deep and narrow through-holes. Although deep
reactive ion etching (DRIE) is widely used for
through-wafer etching [1], the opening size is limited
to several tens of microns, limiting the aspect ratio to
mostly below 20:1. An alternative process for
through-wafer etching is photo-electrochemical
etching, which can produce deep holes with an aspect
ratio greater than 100:1 [4]. However, such VHAR
holes present an unprecedented challenge to fill them
without defects (e.g., holes) by electroplating.
In this paper, we present an approach to fabricate a
dense array of VHAR freestanding metal posts with a
high yield over our entire processing area (3 cm2),
using improved photo-electrochemical etching and
vacuum degassing-assisted electroplating.
FABRICATION
The overall fabrication process, following [2], is
schematically shown in Fig. 1. The first step is to
fabricate the silicon mold with VHAR through-holes
(Fig. 1(a)). N-type (100) silicon wafer with 40-60
Ω-cm resistivity is used. The wafer is etched in 30%
KOH at 78℃ to make the initial V-shape pits by
using an array of square patterns 7 µm in width and
15µm in pitch over the entire processing area. Then,
the sample is etched in 5 wt% HF in DI water (26 ml
of 49% HF in total volume of 300 ml) at room
temperature with backside near infrared (IR)
illumination. A few droplets of a wetting agent
(Kodak Foto-Flo) are added to the electrolyte to help
removing the hydrogen bubbles generated during the
etching, which is very important for VHAR holes
etching. The bias voltage and current density are kept
constant at 2.5 V and 2.0 mA/cm2, independently.
Next, the holes are opened from the backside using
DRIE, and thermal SiO2 is grown to electrically
isolate the silicon surface during the subsequent
metallization. Then, ~50 µm thick nickel layer is
formed on the front side to close the silicon holes
(Fig. 1(b)), providing a seed layer for the subsequent
electroplating step. Next, the holes are filled with a
needed metal by electroplating (Fig. 1(c)). The
freestanding metal posts are finally obtained after
XeF2 etching (Fig. 1(d)).
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Fig. 1: Fabrication process for high-aspect-ratio
micro metal posts.
EXPERIMENTS AND RESULTS
Improved photo-electrochemical etching
For silicon mold, we have made a series of
improvements on photo-electrochemical etching,
including uniform backside ohmic contact, more
accurate feedback control of the etching current, and
modulation of illumination distance. These
improvements enabled us to etch holes with 5 μm
diameter and 15 μm pitch (periodicity) through the
entire 4” wafer thickness (500 μm) by
photo-electrochemical etching (Fig. 2). The 100:1
aspect ratio was limited only by the wafer thickness.
To our knowledge, this is the first demonstrated
through-wafer etching for such high-aspect-ratio
holes for 500 μm wafer. Previously, through-wafer
etching of regular patterns has been limited to either
relatively large (20 μm diameter) holes [1] or thinner
(~300 μm) wafers [5].
Fig. 2: Very-high-aspect-ratio (VHAR) mold by
photo-electrochemical etching (aspect ratio = 100:1).
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Furthermore, the yield and uniformity have been
improved rather dramatically. Figures 3(a) and 3(b)
show the LED source and illumination opening
(processing area ~3 cm2), respectively. The yield of
through-holes over the entire processing area has
improved to ~80% (Fig. 3(c)) from our previous
results of ~30% (Fig. 3(d)). Uniformity is also
excellent, as the diameters and depths near the border
of the processing area are almost identical to those at
the center.
(a) (b)
(c) (d)
Fig. 3: Improvement on yield and uniformity of
VHAR holes by photo-electrochemical etching: (a)
LED source, (b) illumination opening, (c) opposite
surface of high-yield (~80%) through-holes, (d)
opposite surface of previous low-yield (~30%)
through-holes.
Electroplating with vacuum degassing
To fill the 500 μm-deep and 5 μm-diameter pores, we
found the existing electroplating techniques
unsatisfactory, the gas inside the deep pores being the
main culprit. Although successful fillings of high
aspect ratio holes have been reported (e.g., 100:1 and
200 μm deep [5]), none released the metal as
freestanding posts, which demands defect-free filling.
While the yield of through-hole etching is easily
measured by counting the holes on the opposite side,
the yield of filling cannot be assessed thoroughly
until the mold is removed. Figure 4 shows the filling
with a regular plating method. Usually, even when
the metal appeared filling the pores reasonably well
(as most reported in the literature), many were found
missing or defective when freed from the mold (Fig.
4(b)).
 their high yield proving the efficacy of the degassed
plating technique. The high magnification SEM
picture further reveals that the plated nickel is dense
and uniform.

(a)

(b)
Fig. 4: Result of regular (i.e., no vacuum)
electroplating: (a) cross section showing metal in
mold, (b) broken posts after release.

To address the problem, we have developed a plating
apparatus with vacuum degassing, depicted in Fig. 5.
To remove the trapped air before electroplating
started, the pressure was lowered to <60 torr (boiling
point at electroplating temperature ~40℃). During
the plating, the tank was pumped down periodically
(e.g., hourly) to remove H2 accumulation. A
continuous vacuum hurts rather than helps, as a
vacuum makes even small amounts of H2 grow to
form bubbles and block the holes.
Fig. 6: Result of vacuum electroplating, showing
freestanding posts and dense nickel filling.
Figure 7 shows the nickel posts with 5 μm diameter,
15 μm pitch, and 425 μm height (aspect ratio = 85:1),
limited only by the mold thickness. We stopped early
to avoid over-plating. Compared with our previous
result [2], the aspect ratio has increased significantly
(25:1 Æ 85:1), as has the yield (40% Æ 97% over
active areas) and uniformity. The yield over the entire
processing area (3 cm2) was about 80%. The high
yield and uniformity are often more important for
applications. Figure 8 shows the nickel posts firmly
standing on a thin (100 nm) film (Ti/Ni seed) even
when it is warped.

Fig. 5: Schematic illustration of electroplating with

vacuum degassing.

Using the new plating technique, we have succeeded

in obtaining high quality filling. After electroplating a
nickel base layer (~50 μm thick) on one side of the
mold, the holes were filled by electroplating using 5
mA/cm2 in the first hour and 20 mA/cm2 for the
subsequent ~12 hours.

As the silicon mold was removed by XeF2, the nickel

fill finally emerged as freestanding posts (Fig. 6), Fig. 7: Dense array of 425 μm-tall posts

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 Arrays for Three-Dimensional Microbatteries,” J.
Microelectromech. Syst., vol. 16, 2007, pp. 844-852
[3] J. W. Long, B. Dunn, D. Rolison, and H. White,
“Three-dimensional battery architectures,” Chem.
Rev., vol. 104, 2004, pp. 4463–4492
[4] V. Lehmann, “The Physics of Macropore
Formation in Low Doped n-Type Silicon,” J.
Electrochem. Soc., vol. 140, 1993, pp. 2836-2843
[5] L. Wang et al., "High aspect ratio through-wafer
interconnections for 3D microsystems," Proc. IEEE
Int. Conf. MEMS, Kyoto, Japan, Jan. 2003, pp.
634-637

Fig. 8: Nickel posts on 100 nm-thick seed layer.

SUMMARY

High yield (97% on active area and 80% over

processing area) array of VHAR (up to 85:1)
freestanding micro metal posts was obtained by
improved photo-electrochemical etching and vacuum
degassing-assisted electroplating. At this stage, the
aspect ratio can be readily increased from the
reported values by simply using a thicker silicon
wafer and a longer plating. The degassing-assisted
electroplating process will be studied more for a
better understanding and applications for a variety of
micro- and nanostructures.

ACKNOWLEDGEMENT

The authors thank Prof. B. Dunn and his group for

many helpful discussions. This work was supported
by DARPA through Brewer Science and iMINT, UC
Discovery Grant, and Hughes Research Lab. G. Sun
and J. Hur were partly financed by China Scholarship
Council (CSC) and NSF IGERT through MCTP,
respectively.

REFERENCES

[1] C. Gu, H. Xu, and T. Zhang, “Fabrication of High

Aspect Ratio Through-Wafer Copper Interconnects
by Reverse Pulse Electroplating,” J. Micromech.
Microeng., vol. 19, 2009, 065011.
[2] F. Chamran, Y. Yeh, H. Min, B. Dunn, and C.-J.
Kim, “Fabrication of High-Aspect-Ratio Electrode

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