588
3, JUNE 2009
Low-Temperature Monolithic Encapsulation Using
Porous-Alumina Shell Anodized on Chip
Rihui He and Chang-Jin Kim
Abstract—A thin-film encapsulation process, featuring low-
temperature steps, hermetic sealing (preliminary), and RF-
compatible shell, is reported. Uniquely attractive as compared
with the existing MEMS packaging approaches is its capability to
monolithically package metal microstructures inside a microcavity
on chip in one continuous surface-micromachining process. The
key for this process is a technique to fabricate a large freestanding
porous membrane on chip by postdeposition anodization of thin-
film aluminum at room temperature. The porous-alumina mem-
brane allows for the diffusion of gas or liquid etchants through
the nanopores to etch away the sacrificial material underneath,
freeing the movable microstructures encapsulated inside the cav-
ity. To seal the package, a thin film is deposited over the alu-
mina shell whose nanoscale pores of a high aspect ratio (> 30)
do not allow any detectable penetration of the sealing mater-
ial. The low-temperature (< 300 ◦ C) encapsulation process pro-
duced a low-pressure seal (8 torr), monitored by a Pirani pressure
gauge that also represents an encapsulated freestanding metal
microstructure in the cavity. The thin-film package demonstrated
a considerably low RF insertion loss of less than 0.1 dB up to
40 GHz. [2007-0267]
Index Terms—Integrated packaging, low temperature, mono-
lithic encapsulation, porous alumina, RF MEMS packaging, thin-
film encapsulation.
I. I NTRODUCTION
C OMPARED to conventional approaches of packaging an
individual MEMS device in metal or ceramic packages,
wafer-level packaging—packaging the delicate MEMS devices
on wafer before dicing—has long been accepted as the most
effective way to reduce the back-end-of-line cost for a MEMS
product. Hybrid wafer bonding [1]–[7], which employs direct
surface bonding or an intermediate material to bond a sepa-
rate capping wafer to the device wafer, is widely available in
the industry as a mature wafer-level packaging approach. To
address the main drawbacks in hybrid wafer bonding, such as
excessive seal ring width, a thick profile, and the burden of
aligning two wafers, various monolithic thin-film encapsula-
Manuscript received November 4, 2007; revised May 5, 2008, September 5,
2008, December 8, 2008, and February 22, 2009. First published April 24,
2009; current version published June 3, 2009. This work was supported
by the DARPA Harsh Environment Robust Micromechanical Technology
(HERMIT) Program. Subject Editor L. Spangler.
R. He was with the Department of Mechanical and Aerospace Engineering,
University of California, Los Angeles, CA 90095 USA. He is now with
Qualcomm MEMS Technologies, Inc., San Jose, CA 95134 USA (e-mail: rhe@
qualcomm.com).
C.-J. Kim is with the Department of Mechanical and Aerospace Engineering,
University of California, Los Angeles, CA 90095 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JMEMS.2009.2017088
1057-7157/$25.00 © 2009 IEEE
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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 18, NO.
tion processes [8]–[20] have been demonstrated, among which
epitaxial silicon encapsulation is being used in commercial
MEMS resonator products (www.sitime.com). Using thin-film
processes, a sacrificial layer is deposited over an unreleased
device, followed by the deposition of a thin film on top to form
an encapsulation shell layer. Through etch holes opened in the
encapsulation shell by lithography, the sacrificial materials are
selectively removed by wet or dry etching, creating a cavity
and freeing microstructures in it. The cavity is finally sealed
by deposition of a micrometer- to several-micrometer-thick thin
film on the encapsulation shell.
Permeable polysilicon, in situ deposited by low-pressure
chemical-vapor deposition (LPCVD) under a certain condition
[10], [13], and porous polysilicon, formed by postdeposition
electrochemical etching [18], [20], were demonstrated as en-
capsulation shell materials with numerous submicrometer etch
holes. The use of porous encapsulation shell allowed for fast
removal of the sacrificial layers over the entire cavity area
and lessened the issue of the internal deposition of the sealing
material during the sealing process. Inspired by the success of a
porous polysilicon shell in [13], we develop a new nanoporous
thin film in this paper to meet with two essential requirements
of packaging RF MEMS devices—low temperature and low
RF loss. Low-temperature thin-film encapsulation has been
demonstrated by using evaporated Al as a sealing film [21] or
electroplated Ni as a package shell [16]. However, they are not
suitable for RF packaging, as a conductive metal package intro-
duces an RF loss path through the package. Dielectric materials
deposited by sputtering [17] or plasma-enhanced chemical-
vapor deposition (PECVD) [22] and spin-on glass [17] were
used to package RF switches, and such packages showed RF
losses much less than those of the conventional wafer bonding
using solder [23], polymer bonding [24], or thermocompres-
sion [25]–[27].
Noting that aluminum can be deposited at a low temperature
and that it can be anodized to a dielectric material of alumina
with directional nanopores in a similar way as polysilicon
[20], we have developed a process to form a freestanding
porous-alumina membrane through postdeposition anodization
for thin-film encapsulation [28] and reported some initial results
in [29]. A similar method for fabricating a freestanding porous-
alumina membrane for MEMS packaging was reported in a
recent paper [30], where a different etching technique was used
to form a porous-alumina membrane. Here, we consolidate the
incremental results reported in [28] and [29]. Possessing the
benefits of nanoporous thin-film encapsulation [20] and featur-
ing a low-temperature process and extremely low RF loss, the
HE AND KIM: MONOLITHIC ENCAPSULATION USING POROUS-ALUMINA SHELL ANODIZED ON CHIP 589

Fig. 1. Schematic of the pore structure of porous alumina. The pore structure
is a hexagonal array of cylindrical pores, with pore diameter ranging from 10
to 300 nm. An alumina barrier layer is present at the bottom of the pores,
preventing them from growing through the thickness.

porous-alumina thin-film encapsulation process developed in

this paper is potential to be a cost-effective packaging solution
for various MEMS devices, particularly RF devices.

II. D ESIGN AND F ABRICATION

A. Fabrication of Porous-Alumina Membrane
Porous alumina is usually obtained by anodizing bulk alu-
minum foils in a variety of acidic electrolytes such as phos-
phoric acid, sulfuric acid, and oxalic acid. The typical pore Fig. 2. Fabrication process flow of a porous-alumina membrane. Anodization
structure, shown schematically in Fig. 1, is a hexagonal array etching was performed at step (b). The pore morphology change of porous
alumina during anodization etching is shown in Fig. 5 (only the box area defined
of cylindrical pores (pore diameter: 10–300 nm) with a bot- by dashed lines in (b) is displayed).
tom Al2 O3 barrier layer. In a typical (including commercial)
porous-alumina process, the barrier layer is removed by pol-
ishing. For our application, however, the bottom Al2 O3 barrier
layer needs to be removed during the monolithic fabrication
process to allow the etchants to diffuse through the nanopores
and etch away the sacrificial material underneath. Because the
wall thickness between the alumina pores is roughly twice the
thickness of the barrier layer, removing the barrier layer by
isotropic etching would also remove most of the alumina pore
wall. Progressively reducing the anodization voltage [31], [32],
or reversing the bias voltage immediately after the completion
of the anodization etching of Al [33], requires accurate timing
control to stop the etching and is not a reliable process for
fabricating a porous-alumina membrane out of aluminum thin Fig. 3. Schematic view of the anodization etching setup.
film deposited on a partially processed wafer surface.
It is possible to remove the barrier layer but not the alumina 1-μm evaporated Al layer [Fig. 2(a)]. After being diced into
pore wall if the aluminum thin film is deposited on another 2-cm × 2-cm pieces, the samples were placed in a simple
conductive layer. When anodizing the Al thin film deposited custom-made setup (Fig. 3) and anodized at a 40-V constant
on a silicon substrate [34] or an ITO-coated glass substrate bias in a 0.3-mol/L oxalic acid at room temperature [Fig. 2(b)].
[35], the conductive seed layer (silicon or ITO) allowed the Although the anodization was done at the chip level in this
anodization to continue, even after the etching front reached the paper, the same process can be scaled up to the wafer level once
interface, turning the entire Al thin film into porous alumina and the challenge of keeping the anodization etching uniform across
transforming the otherwise thick and attached barrier layer into the wafer is overcome. Fig. 4 shows a typical current variation
numerous thin arches. These thin arches can be removed by an over time during the anodization etching. During the anodiza-
isotropic wet etchant while only widening the pores marginally. tion etching, the current stabilized for a long period, indicating
Using a similar technique, we added a seed layer before the a process of stable pore growth. The pore morphology at the end
aluminum deposition and successfully perforated the bottom of this stage can be observed from an SEM cross section shown
barrier layer in situ. at the top in Fig. 5(b). As the etching continues, the current
A process flow for fabricating the porous-alumina membrane started to increase rapidly, and it was accompanied with gas
is shown in Fig. 2. A stack of thin films on a silicon substrate, bubble generation, signifying that the etching front has reached
from the bottom to the top, consisted of a 0.3-μm PECVD the Au layer where electrolysis would occur. At the same time,
oxide layer for insulation, a 1.5-μm amorphous-silicon (a-Si) the color of the surface started to change from opaque (i.e., the
sacrificial layer, a 1000/100-Å evaporated Ti/Au layer. and a color of aluminum) to translucent and, finally, to transparent.

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590
Fig. 4. Typical curve of current versus time in anodization etching. The
anodization etching was performed on an approximately 2 cm × 2 cm sample
at room temperature. The constant voltage used was 40 V.
Fig. 5. Porous-alumina pore morphology change at the end of anodization
etching and after a wet isotropic etching to remove the bottom barrier layer.
Only the box area of dashed lines in Fig. 2(b) is shown. (a) Schematic view.
(b) SEM cross sections.
The etching was stopped when the surface layer became totally
transparent. The current compliance was set below 100 mA to
reduce the amount of gas bubbles generated at the interface of
porous-alumina and Au layers, where the electrolysis between
the 100-Å Au layer and the H2 O in the anodization etching
solution took place at the end of anodization etching. Without
limiting the current, the pressure built up by the excessive gas
bubbles would have peeled the porous-alumina membrane off
the Au layer. The structure of the bottom barrier layer after
completion of anodization etching is shown in the middle SEM
photograph in Fig. 5(b). A very thin (around 10-nm) arched bar-
rier layer with a small void underneath was observed at the bot-
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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 18, NO. 3, JUNE 2009
Fig. 6. SEM cross-sectional view of a porous-alumina membrane. Note the
flatness of the membrane suspended above the substrate with only a submi-
crometer gap.
tom of each pore. The 100-Å Au layer, sandwiched between the
Ti adhesion layer and the Al layer, is resistant to the electrolyte
during the anodization etching and essential to form an Al2 O3
barrier layer consisting of numerous thin arches. Without the
existence of the Au layer, the Ti adhesion layer would have been
turned into an oxide layer by the electrolyte, which has a similar
pore morphology as that of porous alumina. Thick Ti helps
to distribute the etching current uniformly and thus achieve
uniform pore growth across the entire area of the sample.
The arched thin barrier layer was then removed by a 5-wt%
H3 PO4 wet etching for 25 min, which also widened the pore
to a diameter of 50 nm [bottom SEM photograph of Fig. 5(b)].
Next, the Au and Ti layers beneath the porous alumina were
removed in Au etchant and Ti etchant (a mixture of NH4 OH,
H2 O2 , and H2 O) in the area defined by a photoresist mask
[Fig. 2(c)]. The photoresist mask was intended to remove the
seed layers only in the cavity area so that the porous-alumina
layer in other area was still attached to the substrate. Both the
Au etchant and the Ti etchant have a very high selectivity to
alumina, ensuring no further widening of the pores. It was
found that if the Ti etchant was not well diluted (for example,
NH4 OH : H2 O2 : H2 O = 1 : 1 : 2), a substantial amount of
bubbles would be produced under the porous alumina, pushing
and thus rupturing the porous-alumina membrane. Using a
low-concentrated solution (NH4 OH : H2 O2 : H2 O = 1 : 1 : 8) re-
duced the amount of bubbles significantly, and the Ti layer was
successfully etched away while the porous-alumina membrane
was intact.
After the photoresist mask was stripped, the a-Si sacrificial
layer was etched away by the XeF2 gas, which diffused through
the perforated pores [Fig. 2(d)]. An SEM cross section of the
porous-alumina membrane thus obtained is shown in Fig. 6,
where a 1.5-μm-thick air gap is visible below the alumina.
A magnified view of the cross section of the membrane is
shown in the inset. The transparent porous-alumina membrane
exhibited a very good quality in terms of mechanical and
structural purposes. Porous-alumina membranes as large as
2 mm a side were obtained without any cracks or wrinkles.
Although not tested here directly, it is expected that the
porous-alumina membrane can be fabricated on a wide variety
of substrates, including glass substrates.
B. Encapsulation of a Surface-Micromachined
Metal Microdevice
The hermeticity of the porous-alumina thin-film package was
studied by monitoring the pressure change inside the package
HE AND KIM: MONOLITHIC ENCAPSULATION USING POROUS-ALUMINA SHELL ANODIZED ON CHIP
Fig. 7. Process flow for porous-alumina encapsulation of a Pt Pirani gauge.
through an encapsulated metal Pirani gauge. The Pirani gauge
is a freestanding surface-micromachined device and serves to
represent a typical surface-micromachined metal structure and
to read the vacuum level in situ. The use of Pirani gauge to
monitor the pressure in situ was introduced in [7]–[9] and [16],
and a polysilicon Pirani gauge has successfully been utilized for
polysilicon encapsulation in [20].
The process flow is shown in Fig. 7. First, a 6000-Å silicon
oxide was deposited by PECVD on a silicon substrate for
insulation purposes. Then, a 1-μm a-Si layer was deposited
by PECVD, serving as the sacrificial layer between the Pirani
gauge and the substrate [Fig. 7(a)]. Next, the Pirani gauge
was fabricated by sandwiching 100/400/100-Å Cr/Pt/Cr metal
layers between two layers of 3000-Å low-stress PECVD ox-
ide [Fig. 7(c)], through which release holes were opened by
reactive ion etching. Next, a 4-μm photoresist (AZP 4330)
sacrificial layer was deposited and patterned to define the gap
between the Pirani gauge and the thin-film encapsulation layers
deposited afterward [Fig. 7(d)]. To reduce the outgassing during
the subsequent processes, the photoresist was hard baked at
120 ◦ C in an oven for 20 min, followed by an O2 plasma etching
for 2 min to roughen the surface and improve the adhesion of
metal layers subsequently deposited. The thin-film shell above
the photoresist sacrificial layer consisted of sputtered 3200-Å
Ti layer and evaporated 100/15000-Å Au/Al layer [Fig. 7(e)].
Then, the anodization etching of Al was performed on a
2-cm × 2-cm chip [Fig. 7(f)].
Next, using a photoresist mask, the alumina pores in the cav-
ity area were widened in 5-wt% H3 PO4 etching for 25 min, and
the Ti/Au seed layers were also removed through the pores by
Ti and Au etchants. The photoresist mask, along with the pho-
toresist sacrificial layer below the porous alumina, was removed
by O2 plasma etching [Fig. 7(g)]. Afterward, the a-Si sacrificial
layer under the Pirani gauge was removed by XeF2 plasma
dry etching.
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591
The sealing of the package was achieved by depositing a
PECVD low-stress nitride of 2.5 μm at 300 ◦ C. The deposition
pressure was 500 mtorr. The thickness of the sealing Si3 N4 film
was chosen to prevent physical contact between the package
shell and the Pirani gauge when the package shell is deflected
by the pressure difference as high as ∼1 atm after sealing. The
pressure–deflection relationship [36], [37] is given as
3.41σth 2.45Eth3
p= + (1)
a2 a4
where p is the pressure difference applied on the shell; t,
2a, and h are the thickness, width, and deflection of the
shell, respectively; E is the effective Young’s modulus of the
package shell, which is dominated by that of sealing Si3 N4
(∼190 GPa). Neglecting the residual stress (i.e., σ = 0) and
assuming that the pressure inside the sealed cavity is 0.5 torr
(= PECVD deposition pressure), we estimate that a 2.5-μm-
thick Si3 N4 shell that is 200 μm on a side would deflect around
1.9 μm. This deflection is smaller than the thickness (4 μm)
of the photoresist sacrificial layer with a safety margin of two,
ensuring that the spacing between the shell and the Pirani gauge
is enough under reasonable operation conditions.
Then, the contact pads were opened to obtain electric con-
nection to the Pirani gauge [Fig. 7(h)]. Note that the highest
temperature in the current process was the deposition temper-
ature of the sacrificial and sealing layers by PECVD. If they
were deposited at a lower temperature, the thermal budget for
the entire process would be determined merely by the litho-
graphic steps.
C. RF Performance of a Porous-Alumina Thin-Film Package
Unlike the lithographically defined etch holes [8], [9], [11],
[12], [14], [15], [17], [19], the nanopores with a very high
aspect ratio in this paper do not allow the sealing material
592
Fig. 8. Test process to detect the penetration of the sealing material through porous alumina. To remove the native oxide, the silicon substrate was cleaned
by hydrofluoric acid before the Ti deposition. The oxide deposition was performed in PECVD. The porous-alumina layer of two thicknesses (0.5 and 1.0 µm)
was tested.
Fig. 9. Process flow for porous-alumina encapsulation of a CPW line.
to pass through them, effectively preventing its deposition
inside the cavity. It was studied experimentally in [14] that
the amount of sealing material (PECVD thin film) deposited
inside the cavity was dependent on the aspect ratio of the
release holes. The authors concluded that no internal deposition
of the sealing material would occur if the aspect ratio (i.e.,
depth to diameter) of the release holes remains above four
when the release holes are 0.35 μm in diameter. Given that an
aspect ratio over ten (e.g., 0.5-μm-thick porous alumina with
pores of diameter below 50 nm) can be easily obtained for
the pores of porous alumina, it is anticipated that no sealing
material would diffuse through the pores and deposit on the
device surface inside the package. An experiment was carried
out to confirm our claim. The test sample has a configuration,
as shown in Fig. 8(a). The porous-alumina cavity was formed
on a silicon substrate by removing the 5000-Å Ti sacrifi-
cial layer through the nanopores. Porous-alumina membranes
of two different thicknesses, namely, 5000 Å and 1.5 μm,
were fabricated. A pore aspect ratio ranging from 10 to 25 was
obtained by changing the pore size through controlling the time
in the widening process of the pores in 5-wt% H3 PO4 . After
being sealed by a 5000-Å PECVD oxide deposition, as shown
Fig. 8(b), the cavity was ruptured using a probe tip, and the
thickness of oxide on top of the silicon substrate inside the
cavity was measured by Nanospec with a thin oxide program
(low limit: 20 Å). For all the samples tested, a “less than
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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 18, NO. 3, JUNE 2009
20-Å” result was obtained, indicating that the porous-alumina
shell effectively prevented the internal deposition of the sealing
material during the sealing process.
To investigate the RF performance of the porous-alumina
thin-film package, a coplanar waveguide (CPW) device was fab-
ricated and packaged, following the fabrication process shown
in Fig. 9. The process starts with 6000-Å thermal oxidation, as
well as 3000-Å LPCVD silicon nitride deposition, to insulate
the CPW line from the substrate [Fig. 9(a)]. A silicon wafer
with high resistivity (> 2000 Ω · cm) was chosen to reduce the
RF loss through the substrate. The subsequent liftoff process of
Cr/Au 200/8000 Å formed a CPW line [Fig. 9(b)]. The dimen-
sion of CPW lines was designed and simulated using a commer-
cial software (HFSS). The next step was PECVD depositions of
1-μm SiO2 and 1.8-μm a-Si sacrificial layer [Fig. 9(c)]. Then, a
1000/100-Å Ti/Au seed layer was evaporated and patterned by
the liftoff process [Fig. 9(d)], followed by 1-μm Al evaporation
[Fig. 9(e)]. The wafer was diced into chips with a size of
around 2 cm × 2 cm. Following the procedure described earlier,
the Al thin film on the entire chip was turned into porous
alumina by the anodization etching [Fig. 9(f)], and the porous-
alumina cavity was formed by removing the Ti/Au seed layer
and the a-Si sacrificial layer sequentially [Fig. 9(g)]. A PECVD
deposition of 1-μm low-stress silicon nitride sealed the device
[Fig. 9(h)]. The final step was etching away all the films above
Au in the electrical contact area.
HE AND KIM: MONOLITHIC ENCAPSULATION USING POROUS-ALUMINA SHELL ANODIZED ON CHIP
Fig. 10. Monolithically encapsulated metal Pirani gauge. (a) Optical micro-
graphic top view of a packaged Pirani gauge. Note that the encapsulation shell,
consisting of 1.5-µm porous alumina and 2.5-µm silicon nitride sealing film, is
transparent. (b) SEM photograph of a porous-alumina package intentionally
ruptured to expose the Pirani gauge. (c) Cross-sectional SEM photograph
showing the silicon nitride sealing layer, the porous-alumina layer, as well as a
suspended metal (Pt) Pirani gauge.
III. R ESULTS
A. Encapsulation of Surface-Micromachined
Metal Microdevice
Shown in Fig. 10(a) is an optical microscope top view of the
package with a Pt Pirani gauge encapsulated inside. The en-
capsulated Pirani gauge is clearly seen through the transparent
porous-alumina shell and silicon nitride seal. From the angled
SEM photograph of Fig. 10(b), the Pirani gauge is shown
freestanding after the shell was intentionally ruptured. From
the SEM photograph of Fig. 10(c), the cross-sectional details
of all the layers, including the porous-alumina shell, the sealing
nitride, and the Pirani gauge, could be observed on a cleaved
sample. The cross-sectional view confirms that the Pirani gauge
is suspended approximately 1 μm over the substrate.
The pressure inside the sealed cavity was measured from the
encapsulated Pt Pirani gauge. We followed a procedure similar
to that used for the polysilicon Pirani gauge [20] to calibrate
the Pt Pirani gauge and monitor the internal pressure inside
the package. The resistance-versus-current characteristics of
a Pirani gauge were first obtained while it was encapsulated.
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593
Fig. 11. Resistance-versus-current characteristics of a Pirani gauge. The
pressure inside the sealed device is extracted to be around 8 torr.
Fig. 12. Pressure change of two different sealed cavities fabricated on differ-
ent chips.
After breaking the seal, the entire sample was then placed in a
pressure-controlling chamber, where the gauge was calibrated
against known pressures. The pressure inside the sealed cavity,
extracted by matching the resistance–current curve of the Pirani
gauge while sealed with the calibration data (Fig. 11), was
around 8 torr, a value that is much larger than the deposition
pressure of the PECVD silicon nitride sealing film—0.5 torr.
This discrepancy is speculated to be due to the outgassing
from the residual photoresist left inside the package. A few
ideas, including an extensive baking before the deposition of the
sealing film, may be tried, if necessary in the future, to obtain a
lower pressure inside the cavity. A preliminary evaluation of the
package hermeticity was obtained from the thermal impedance
changes of two sealed Pirani gauges, a method that was used
in [7] and [16]. As shown in Fig. 12, the pressure inside the
sealed packages has shown a less than 0.4-torr increase for
15 days. The testing was terminated after a short term because
of logistic, rather than technical, reasons. We noted that one
594 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 18, NO. 3, JUNE 2009

Fig. 13. Encapsulated CPW device. The Au signal line is clearly visible through the transparent porous-alumina shell in (a). Schematic cross-sectional views are
shown in (b) and (c). The a-Si, left to serve as electric feedthrough, turns out to be the main source of RF insertion loss.

of the devices showed a pressure decrease inside the cavity

after 12 days. This could be due to the fluctuation of ambient
temperature as the performance of the Pirani gauge is sensitive
to the temperature change. Another possible reason is that the
outgass from the traces of photoresist became absorbed on the
interior surface of the porous alumina. A long-term hermeticity
study of varying device configurations is desired in the future.

B. RF Performance of a Porous-Alumina Thin-Film Package

An optical microscopic top view of a fabricated device
for evaluating the RF performance is shown in Fig. 13(a). A
160-μm × 300-zμm sealed cavity is seen in the middle of the
photograph. The Au signal line encapsulated inside the sealed
cavity is clearly visible through the transparent encapsulation
shell, which is composed of 1.2-μm porous alumina and 1-μm
silicon nitride thin films. The schematic views of the cross
section of the devices along the A−A and B−B direction
are shown in Fig. 13(b) and (c), respectively. The SEM cross
section in Fig. 13(b) shows the porous alumina, along with
the silicon nitride sealing film, suspending over the Au signal
line by a gap of around 3 μm. Amorphous silicon was used
to separate the encapsulation shell and the Au CPW lines in the
feedthrough area. The cross section can be seen in the schematic
figure of a B−B cross section and the SEM photograph in
Fig. 13(c).
Fig. 14. (Left axis) Insertion loss difference—less than 0.1 dB up to
40 GHz—between packaged and unpackaged CPW devices demonstrates that
the reported encapsulation has a very small influence on the performance of an
RF device.
The influence of the package on the CPW lines was in-
vestigated by measuring the S-parameter matrix of a naked
CPW transmission line and a packaged CPW transmission line.
The measurement was conducted using an HP/Agilent 8510C
network analyzer. Before the measurement, a calibration was
performed on a calibration substrate using the probes and the
software from GGB Industries, Inc. Fig. 14 shows the measured
insertion loss (S21), as well as the return loss (S11), of both

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HE AND KIM: MONOLITHIC ENCAPSULATION USING POROUS-ALUMINA SHELL ANODIZED ON CHIP
Fig. 15. Influence of feedthrough length on insertion loss. The package with
50-µm-long feedthrough was measured to have more insertion loss than the
package with 20-µm-long feedthrough.
packaged and unpackaged CPW transmission lines. It is shown
that the insertion loss introduced by the package is less than
0.1 dB up to 40 GHz. The insertion loss of the packaged CPW
transmission line follows that of the naked CPW transmission
line very well without any resonance or peak occurring across
the band of the measurement. For the return loss, there is barely
any discernable difference. The length of the feedthrough was
found to have an impact on the RF performance of the pack-
age. The insertion losses of the two packages with different
feedthrough lengths, namely, 20 and 50 μm, were measured and
are shown in Fig. 15. A larger insertion loss was evident on the
packaged device with a feedthrough length of 50 μm, indicating
that a shorter feedthrough is desirable when designing the
package. It can be inferred from this measurement that the small
0.1-dB insertion loss introduced from the package is due to the
silicon sacrificial layer left in the feedthrough area [Fig. 13(c)].
Removing this sacrificial layer in the feedthrough by adding
an extra lithography and etching step could potentially further
reduce the insertion loss of the package.
IV. C ONCLUSION
A porous-alumina thin film, obtained by the anodization
etching of evaporated or sputtered aluminum thin film at room
temperature, was discovered to be an excellent choice as an
encapsulation shell for low-temperature on-wafer monolithic
packaging. A surface-micromachining process, combined with
anodization etching, was developed to fabricate a large free-
standing porous-alumina thin-film shell. The barrier layer at
the bottom of the nanopores was successfully perforated by
extending the anodic etching with the help of a conductive seed
layer and a short wet etching. A porous-alumina monolithic
encapsulation was successfully developed to seal a surface-
micromachined metal Pirani gauge at a low pressure (8 torr),
and the package has demonstrated moderate hermeticity in a
preliminary (i.e., short-term) characterization run. The influ-
ence of the porous-alumina thin-film package on the RF per-
formance of MEMS devices was measured to be considerably
low—less than 0.1-dB insertion loss up to 40 GHz.
Authorized licensed use limited to: Univ of Calif Los Angeles. Downloaded on June 8, 2009 at 17:36 from IEEE Xplore. Restrictions apply.
595
ACKNOWLEDGMENT
The authors would like to thank J.-K. Park for his help with
anodization etching.
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Rihui He received the B.S. degree (with high honors) from the University
of Science and Technology of China, Hefei, China, in 1998, the M.S. degree
from Tsinghua University, Beijing, China, in 2000, and the Ph.D. degree
in mechanical and aerospace engineering from the University of California,
Los Angeles, in 2005.
He is currently with Qualcomm MEMS Technologies, Inc., San Jose, CA.
His research interests include MEMS wafer-level packaging, as well as design
and fabrication of microsensors and microactuators.
Chang-Jin “CJ” Kim received the B.S. degree from Seoul National University,
Seoul, Korea, the M.S. degree from Iowa State University, Ames, and the Ph.D.
degree in mechanical engineering in 1991 from the University of California,
Berkeley.
Since joining the faculty at the University of California, Los Angeles
(UCLA), in 1993, he has developed several MEMS courses and established
a MEMS Ph.D. major field in the Department of Mechanical and Aerospace
Engineering. Directing the Micro and Nano Manufacturing Laboratory, he is
also an IRG Leader for the NASA-supported Institute for Cell Mimetic Space
Exploration and a Founding Member of the California NanoSystems Institute,
UCLA. His research includes MEMS and nanotechnology, including design
and fabrication of micro/nano structures, actuators, and systems, with a focus
on the use of surface tension. He has served on numerous Technical Program
Committees, including Transducers and the IEEE MEMS Conference, and
has served on the U.S. Army Science Board as Consultant. He is currently
the Chairman of the Devices and Systems Committee of the ASME Nano-
technology Institute and serving as a Subject Editor for the JOURNAL OF
MICROELECTROMECHANICAL SYSTEMS, on the Editorial Advisory Board of
the IEEJ Transactions on Electrical and Electronic Engineering, and on the
National Academies Panel on Benchmarking the Research Competitiveness of
the U.S. in Mechanical Engineering.
Prof. Kim was the recipient of the 1995 TRW Outstanding Young Teacher
Award, the 1997 NSF CAREER Award, the 2002 ALA Achievement Award,
and the Graduate Research Excellence Award.