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September 2001 Computer Hardware Lecture 11 Slide1 September 2001 Computer Hardware Lecture 11 Slide2
We have also used registers in our synchronous The state register had a common clock for all the flip
design method to store the state of a finite state flops:
machine.
b3 b2 b1 b0
A set of n flip-flops can represent 2n states
D Q D Q D Q D Q
Clock
September 2001 Computer Hardware Lecture 11 Slide3 September 2001 Computer Hardware Lecture 11 Slide4
Inside a computer data is organised in a parallel form. Register are used to convert data from serial form to
parallel form.
Thus a data register containing say 32 flip flops will
have a common clock, and all 32 bits will be set at the Each successive bit is read on a falling clock edge.
same time
Clock
time
September 2001 Computer Hardware Lecture 11 Slide5 September 2001 Computer Hardware Lecture 11 Slide6
A four bit serial to parallel convertor Timing serial Input
September 2001 Computer Hardware Lecture 11 Slide7 September 2001 Computer Hardware Lecture 11 Slide8
to the D-types b3 b2 b1 b0
Parallel In
September 2001 Computer Hardware Lecture 11 Slide9 September 2001 Computer Hardware Lecture 11 Slide10
A
It can be made up from AND and OR gates
Out
September 2001 Computer Hardware Lecture 11 Slide11 September 2001 Computer Hardware Lecture 11 Slide12
Four bit shift register Multiplying and Dividing by 2
September 2001 Computer Hardware Lecture 11 Slide13 September 2001 Computer Hardware Lecture 11 Slide14
We saw how to make a register perform two Our next example will be a shift register with the
functions: following four functions:
September 2001 Computer Hardware Lecture 11 Slide15 September 2001 Computer Hardware Lecture 11 Slide16
We can give a shift register four functions by using a A binary to unary convertor simply calculats all
four way multiplexor (switch) to select the D input to minterms of the inputs. For one input, only one output
the flip-flops is non zero.
B1 U3
B0
Designing a four way multiplexer is similar to the two
way multiplexer, but we will do it in two stages to U2
generalise the design
U1
U0
September 2001 Computer Hardware Lecture 11 Slide17 September 2001 Computer Hardware Lecture 11 Slide18
Four way multiplexer Connecting up the shift register
Given a binary to unary convertor, the multiplexer
can be built trivially by providing a gating circuit. We can make the shift register as long as we like.
S1 S0
Binary to Unary Convertor
Multiplexer Control
B1 B0 S1
Gating circuit S0
U3 U2 U1 U0
MUX D Q MUX D Q MUX D Q
&c. &c.
A
B
Out Clock
Stage i+1 Stage i Stage i-1
C
D
September 2001 Computer Hardware Lecture 11 Slide19 September 2001 Computer Hardware Lecture 11 Slide20
Clock
PIi
September 2001 Computer Hardware Lecture 11 Slide21 September 2001 Computer Hardware Lecture 11 Slide22
September 2001 Computer Hardware Lecture 11 Slide23 September 2001 Computer Hardware Lecture 11 Slide24
Clocks and Watches 2 Divide by 256
We could use a synchronous circuit to do this, but, it Dividing by 16 can be easily designed synchronously.
would require a synchronous counter with 106 states, Cascading two dividors gives us dived by 256
and therefore 20 D-Q flip-flops!
Clk in
September 2001 Computer Hardware Lecture 11 Slide25 September 2001 Computer Hardware Lecture 11 Slide26
This delightfully simple counter can be arbitrarily Suppose that we wish to divide a clock by a number
large, but it is not synchronous. which is not a power of two.
September 2001 Computer Hardware Lecture 11 Slide27 September 2001 Computer Hardware Lecture 11 Slide28
clk
We can get out circuit to count to 0,1,2,3,4, but as
soon as we detect 5 on the output we reset all the Q
values to 0.
Out
September 2001 Computer Hardware Lecture 11 Slide29 September 2001 Computer Hardware Lecture 11 Slide30