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Table Of Contents

Tutorial Contents
Tutorial Flows
•HDL Design Flow
•Schematic Design Flow
HDL Design Flow
Schematic Design Flow
Implementation-only Flow
Additional Resources R
Additional Resources
Overview of ISE
•“Overview of ISE”
Project Navigator Interface
Design Panel
Sources View
Processes View
Files Panel
Libraries Panel
Console Panel
Errors Panel
Warnings Panel
Error Navigation to Source
Error Navigation to Answer Record
Design Summary & Report Viewer
Using Project Revision Management Features R
Using Project Revision Management Features
ISE Project File
Making a Copy of a Project
Using the Project Browser
Using Project Archives
Creating an Archive
Restoring an Archive
HDL-Based Design
•“Overview of HDL-Based Design”
•“Getting Started”
Overview of HDL-Based Design
Getting Started
Required Software
Optional Software Requirements
VHDL or Verilog?
Installing the Tutorial Project Files
Starting the ISE Software
Creating a New Project
Creating a New Project: Using the New Project Wizard
Design Description R
Stopping the Tutorial
Design Description
Functional Blocks
Design Entry
Adding Source Files
Checking the Syntax
Correcting HDL Errors
Creating an HDL-Based Module
Using the New Source Wizard and ISE Text Editor
To create a CORE Generator module:
Instantiating the CORE Generator Module in the HDL Code
Creating a DCM Module
Using the Clocking Wizard
Instantiating the dcm1 Macro - VHDL Design
Instantiating the dcm1 Macro - Verilog
Synthesizing the Design
Synthesizing the Design using XST
Entering Synthesis Options
To enter synthesis options:
The RTL / Technology Viewer
Synthesizing the Design using Synplify/Synplify Pro
Examining Synthesis Results
•“Compiler Report”
•“Mapper Report”
•“Timing Report”
Compiler Report
Resource Utilization
Synthesizing the Design Using Precision Synthesis
Entering Synthesis Options through ISE
The RTL/Technology Viewer
Schematic-Based Design
•“Overview of Schematic-Based Design”
Overview of Schematic-Based Design
Creating a New Project: Using New Project Wizard
Opening the Schematic File in the Xilinx Schematic Editor
Adding Schematic Components
Correcting Mistakes
Drawing Wires
Adding Buses
Adding Bus Taps
Adding Net Names
Checking the Schematic
Saving the Schematic
Creating and Placing the time_cnt Symbol
Creating the time_cnt symbol
Placing the time_cnt Symbol
Creating the dcm1 Symbol
Creating Schematic Symbols for HDL modules
Placing the statmach, timer_preset, dcm1 and debounce Symbols
Changing Instance Names
Hierarchy Push/Pop
Specifying Device Inputs/Outputs
Adding Input Pins
Adding I/O Markers and Net Names
Assigning Pin Locations
Completing the Schematic
Behavioral Simulation
•“Overview of Behavioral Simulation Flow”
•“ModelSim Setup”
Overview of Behavioral Simulation Flow
ModelSim Setup
ModelSim PE and SE
ModelSim Xilinx Edition
ISim Setup
Required Files
Design Files (VHDL, Verilog, or Schematic)
Test Bench File
Xilinx Simulation Libraries
Updating the Xilinx Simulation Libraries
Mapping Simulation Libraries in the Modelsim.ini File
Adding an HDL Test Bench
Adding Tutorial Test Bench File
VHDL Simulation
Verilog Simulation
Behavioral Simulation Using ModelSim
Locating the Simulation Processes
Specifying Simulation Properties
Performing Simulation
Adding Signals
Adding Dividers
Analyzing the Signals
Saving the Simulation
Behavioral Simulation Using ISim
Rerunning Simulation
Design Implementation
•“Overview of Design Implementation”
Overview of Design Implementation
Continuing from Design Entry
Starting from Design Implementation
Specifying Options R
Specifying Options
Creating Timing Constraints
Translating the Design R
Translating the Design
Using the Constraints Editor
Assigning I/O Locations Using PlanAhead
Mapping the Design R
Mapping the Design
Using Timing Analysis to Evaluate Block Delays After Mapping R
Using Timing Analysis to Evaluate Block Delays After Mapping
Estimating Timing Goals with the 50/50 Rule
Report Paths in Timing Constraints Option
Placing and Routing the Design R
Placing and Routing the Design
Using FPGA Editor to Verify the Place and Route
Evaluating Post-Layout Timing
•Viewing the Post-Place & Route Static Timing Report
Viewing the Post-Place & Route Static Timing Report
Analyzing the Design using PlanAhead
Creating Configuration Data
Creating a PROM File with iMPACT
Command Line Implementation R
Command Line Implementation
Chapter 6
Timing Simulation
•“Overview of Timing Simulation Flow”
Overview of Timing Simulation Flow
Specifying a Simulator
Timing Simulation Using ModelSim
Specifying Simulation Process Properties
Timing Simulation Using Xilinx ISim
Viewing Full Signal Names
iMPACT Tutorial
•“Device Support”
Device Support
Download Cable Support
Parallel Cable IV
Platform Cable USB
MultiPRO Cable
Configuration Mode Support
Generating the Configuration Files
Creating a iMPACT New Project File R
Connecting the Cable
Starting the Software
Opening iMPACT from Project Navigator
Opening iMPACT stand-alone
Creating a iMPACT New Project File
Using Boundary Scan Configuration Mode
Specifying Boundary Scan Configuration Mode
Assigning Configuration Files
Saving the Project File
Editing Preferences
Troubleshooting Boundary Scan Configuration
Verifying Cable Connection
Verifying Chain Setup
Slave Serial Configuration Mode
SelectMAP Configuration Mode
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Published by Igor Alexis

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Published by: Igor Alexis on Jun 03, 2011
Copyright:Attribution Non-commercial


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