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Table Of Contents

From software to hardware
2.2.3 Objects
2.3 Structured programming
2.3.1 Primitives
2.3.2 Constructs
2.3.3 Partitions
2.4 Standard programming languages
2.4.1 Modula 2
3.1.1 Translation from programming language
3.1.2 Structure
3.1.3 Interpretation
3.1.4 Instructions
3.1.5 Operands
3.2 Simple architectures
3.2.1 Sequential processing
3.2.2 Parallel processing
3.2.3 Modular software
3.3 Instruction set complexity
3.3.1 Reduced instruction set computer (RISC)
3.3.2 Complex instruction set computer (CISC)
3.3.3 Comparison of RISC and CISC
From switches to processors
4.1.1 Pure binary
4.1.2 Hexadecimal
4.2 Primitive data types
4.2.1 Integer
4.2.2 Character
4.3 Structured data types
4.3.1 Sequence association
4.3.2 Pointer association
5.1 Combinational systems
5.1.1 Specification
5.1.2 Physical implementation
5.1.3 Physical properties
5.2 Sequential systems
5.2.1 Physical nature
5.2.2 Specification
5.2.3 Physical implementation
5.2.4 Physical properties
6.1 Combinational system design
6.1.1 Boolean algebra
6.1.2 Karnaugh maps
6.1.3 Quine-McCluskey
6.2 Sequential system design
6.2.1 Moore machines
6.2.2 Mealy machines
6.2.3 Summary
6.3 Components
6.3.1 Logic units
6.3.2 Arithmetic logic units
6.3.3 Registers
7.1 Function of the control unit
7.1.1 Processor organization
7.1.2 Machine language interpretation
7.1.3 Fetch/execute process
7.2 Implementation
7.2.1 Introduction
7.2.2 Minimum state method
7.2.3 Shift register method
7.2.4 Counter method
8.1.1 General requirements
8.1.2 Throughput
8.1.3 Real-time systems
8.2 Accumulator machine
8.2.1 Programming constructs
8.2.2 Data referencing
8.2.3 Booting
8.2.4 Summary
8.3 Stack machine
8.3.1 Software partitions
8.3.2 Data referencing
8.3.3 Expression evaluation
8.3.4 Alternation
8.3.5 Summary
8.4 Register window + instruction cache machine
8.4.1 Exploitation of locality
8.4.2 Software partitions
8.4.3 Data referencing
8.4.4 Parallel instruction execution
8.4.5 Summary
8.5.1 Process scheduling
8.5.2 Message passing
8.5.3 Alternation
8.5.4 Summary
9.1 Internal communication
9.1.1 System bus
9.1.2 Bus arbitration
9.1.3 Synchronous bus transactions
9.1.4 Asynchronous bus transactions
9.2 Memory organization
9.2.1 Physical memory organization
9.3.1 Event driven memory mapped I/O
9.3.2 External communication (I/O) processors
Chapter 10 Survey of contemporary processor architecture
10.1 Introduction
10.2 Motorola 68000
10.2.1 Architecture
10.2.2 Organization
10.2.3 Programming
10.3 National Semiconductor 32000
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Computer Architecture and Organization _._ Ian East

Computer Architecture and Organization _._ Ian East

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Published by Hùng Nguyen

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Published by: Hùng Nguyen on Jun 03, 2011
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11/24/2012

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