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A Low-Power CMOS Programmable CNN Cell and its Application to Stability of CNN with Opposite-Sign Templates

A Low-Power CMOS Programmable CNN Cell and its Application to Stability of CNN with Opposite-Sign Templates

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Published by ijcsis
In this paper, a novel VLSI architecture adaptation of the Cellular Neural Network (CNN) paradigm is described. It is based on a combination of MOS transistors operating in weak inversion regime. This combination has enabled a CMOS implementation of a simplified version of the original CNN model with the main characteristics of low-power consumption. Digitally selectable template coefficients are employed and a local logic and memory are added into each cell providing a simple dual computing structure (analog and digital). A four-quadrant analog multiplier is used as a voltage controlled current source which is feeding from the weighting factors of the template elements. The main feature of the multiplier is the high value of the weight voltage range which varies between the ground voltage and the supply voltage. A simulation example for stability of a class of nonreciprocal cellular neural network with opposite-sign template is presented.
In this paper, a novel VLSI architecture adaptation of the Cellular Neural Network (CNN) paradigm is described. It is based on a combination of MOS transistors operating in weak inversion regime. This combination has enabled a CMOS implementation of a simplified version of the original CNN model with the main characteristics of low-power consumption. Digitally selectable template coefficients are employed and a local logic and memory are added into each cell providing a simple dual computing structure (analog and digital). A four-quadrant analog multiplier is used as a voltage controlled current source which is feeding from the weighting factors of the template elements. The main feature of the multiplier is the high value of the weight voltage range which varies between the ground voltage and the supply voltage. A simulation example for stability of a class of nonreciprocal cellular neural network with opposite-sign template is presented.

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A Low-Power CMOS Programmable CNN Cell andits Application to Stability of CNN with Opposite-Sign Templates
S. El-Din, A. K. Abol Seoud, and A. El-Fahar
Electrical Engineering DepartmentUniversity of AlexandriaAlexandria, Egypt.E-mail: eng_salah_alx@yahoo.com
 Abstract
--In this paper, a novel VLSI architecture adaptation of the Cellular Neural Network (CNN) paradigm is described. It isbased on a combination of MOS transistors operating in weakinversion regime. This combination has enabled a CMOSimplementation of a simplified version of the original CNNmodel with the main characteristics of low-power consumption.Digitally selectable template coefficients are employed and alocal logic and memory are added into each cell providing asimple dual computing structure (analog and digital). A four-quadrant analog multiplier is used as a voltage controlledcurrent source which is feeding from the weighting factors of thetemplate elements. The main feature of the multiplier is the highvalue of the weight voltage range which varies between theground voltage and the supply voltage. A simulation example forstability of a class of nonreciprocal cellular neural network withopposite-sign template is presented.
 Keywords: Cellular Neural Network, Low-power CNN, Opposite-Sign Template.
I. INTRODUCTIONCellular Neural Networks (CNNs), introduced by Chua andYang in 1988 [1], have been extensively studied in the pasttwo decade [2, 3, 4]. All such studies have been focused onfour special topics: 1) the CNN functions; 2) hardwareimplementation; 3) software systems; and 4) variousengineering and scientific applications [5]. CNNs have beensuccessfully applied to signal processing systems, especiallyin static image treatment [3], and to solve nonlinear algebraicequations [6]. It has also been shown that the process of moving images requires the introduction of time delays in thesignals transmitted through the network [7,8,9].Through VLSItechnology and using switching circuit techniques such delayscan be introduce in the interaction between neurons [8]. Torealize the CNN on a silicon chip, the CNN cell is required tohave low power consumption. Various analog VLSIimplementations of CNN building locks have been previouslyimplemented and tested [10, 11]. Such implementations haveserved to build CNNs under different constraints concerningthe size of the network, the kind of cell input and state(analog/digital), the power consumption, and theprogrammability features of the network allowing morecompact VLSI implementations [12].The aim of this paper is to design and implement a newlow-power CMOS CNN cell. The circuit employs low-
 
M. El-Sayed Ragab
School of Electronics, Comm. and Computer Eng.E-JUST.Alexandria, Egypt.E-mail: m.ragab@ejust.edu.egpower four quadrant multipliers using MOSFET's operating inthe weak inversion regime, where the small currentscontribute to the low- power consumption [13]. The multiplieralso has a variable transconductance characteristic for theprogrammability of the CNN structure. The proposed cell hasbeen applied to study the stability [14, 15], and oscillation of aCNN paradigm [16, 17]. The performance of the proposedcircuit has been evaluated using PSPICE simulations.II. The General Framework 
 
A cellular neural network [1] is a special type of neuralnetworks, where the analog processing elements on one layerare arranged in a two-dimensional grid having cellinterconnections with nearest neighbors only. Consider theanalog processing cell circuit, henceforth called a cell, asshown in Fig.1(a), with only one nonlinear element whosecharacteristics is shown in Fig.1(b). This cell is located in the( i , j ) position of a two-dimensional regular array of 
 N  M 
 cells. The r-neighborhood
 ji
 N 
,
of a typical cell
 ji
,
 is defined as:
)(,max,,,
eger in jlil ji
 N 
(1)An
=1 neighborhood of a cell within a cell array consists of all those cells shown shaded in Fig.1(c).
( a )(b)
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 5, May 201143http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
 
( c )Figure 1. The cell circuit model and its neighborhood in a cell array. (a) Thecell circuit model (b) The characteristics of the single nonlinear element of the cell (a voltage-controlled current source). (c) An r =1 neighborhood in apart of a cell array.
The dynamical system equations describing a cellular neuralnetwork consist of the following equations and constraints:(1) State Equation:
 I  N l ji B  N l ji A dt 
 RdV 
ukl jil  jil  ykl xij x xij
)(),;,( )(),;,()( 1
),(),( ),(),(
(2)where
 N  j M i
1;1
 (2) Output Equation:
).(1)(1)(5.0)(
xij xij xij yij
(3)(3) Input Equation:
.
 E 
ijuij
(4)(4) Constraint Equations:
1)0(
 xij
(5)
.1
uij
(6)(5) Parameter Assumptions:
),;,(),;,(
jil Al ji A
Symmetry condition (7)
.0,0
 R
 x
(8)III. Stability of Cellular Neural NetworksA necessary condition for the proper operation of a cellularneural network is that it be completely stable within thedynamic range of prescribed inputs. A circuit is said to becompletely stable if every trajectory tends to an equilibriumstate. The complete stability of a subclass of cellular neuralnetworks is defined by symmetric templates [1]. Thesymmetry condition means that the feedback values betweenany two cells are reciprocal in the sense that correspondingvalues are the same; i.e.,
),;,(),;,(
jil Al ji A
. Theassumption ( 7 ) implies the perfect symmetry of thefeedback-template values between any two cells within aneighborhood. From theorem 4 in [1], if the parameters satisfythe symmetry condition, the circuit will be completely stable.But many unsymmetrical templates have been found for some
 
important applications [3]. In [14] it has been shown that for aclass of practically important templates (positive / negative
 
and opposite-sign templates), the complete stability
 
propertyis assured even if the symmetry condition is not met. In [15] athrough stability analysis of cellular neural networks withopposite-sign templates has been presented. In this analysis,the dependence of complete stability on the template values,and the parameter regions for complete stability andinstability have been determined. This class is defined by thetemplate values which satisfy the following structures andsign conditions [14]:
000000
s ps A
(9)where
 R
 x
 p
1
and
0
s
 The complete stability of the system defined by (2) has beenproven to be strongly conjectural if [15]:
)1(2)1()0)
ps pii Bi
(10)Also, the network will oscillate periodically if [16]:
1)0)
psii Bi
(11)IV. Low-Power CMOS Programmable CNN CellThe block diagram of a continuous time CNN cell is shownin Fig.2.
Figure2
.
Block diagram of CNN cell.
Vx
ij
is the state of cell C
ij
, with an initial condition Vx
ij
(0),R
x
C conforms the integration time constant of the system. Thecell output is Vy
ij
(t) =
 f 
(Vx
ij
(t)), where
 f 
can be anyconvenient non-linear function. The block A can beimplemented using a set of four quadrant multipliers whoseinputs are the outputs of the cells within the assumedneighborhood and the template A values. Similarly, block Bcan be implemented using a set of four quadrant multiplierswhose inputs are the inputs of the cells within the assumedneighborhood and the template B values. The outputs of blocks A and B are (in the current form) Ixy and Ixu,respectively. Those currents are summed with the bias currentI of the cell and then integrated in the R
x
C circuit, to result inthe cell state voltage Vx
ij
. The output voltage of the cell Vy
ij
isobtained through the limiting transfer function
 f 
(Vx
ij
).Alternatively, the nonlinear transfer function
 f 
(Vx
ij
) can beincorporated in the multiplier circuits themselves, resulting ina small area CNN cell. This can be realized using low-powerCMOS four quadrant multipliers operating in weak inversionregime.
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 5, May 201144http://sites.google.com/site/ijcsis/ISSN 1947-5500
 
BB0 B1 B2 B3B4
I0I0I1 I2 I3 I4VddVggIbV1 V2V3 V3
I1I2Io
VddVddV4VddVddVa
 
A. Programmable Low-power CMOS four quadrantmultiplierFig. 3 shows the proposed programmable low-power CMOSfour quadrant multiplier circuit and its sub-circuitrepresentation.
 
 
(a)(b)Figure 3. (a) Four quadrant multiplier schematic (b) Multiplier sub-circuitrepresentation
This circuit represents a trade-off between digital and analogtechniques. It is composed of registers which store the weightvalues, a linear DAC and a tranconductance multiplier. TheDAC has five bits plus sign weight storage which sets the tailbias current I
b
. The least significant bit bias current has beenset to 40 pA. The DAC has shown good monotonicity in theweak inversion regime. Each bit (B0-B4) of the DAC iscontrolled by a pass transistor which can be turned on or off depending on the value stored in the corresponding CMOSlatch.I0-I4 are the current sources which contribute to the biascurrent I
b
in a successive power of two fashion. The DAC isconnected to a transconductance amplifier to form a fourquadrant multiplier. Assuming weak inversion operation forall MOS devices in the multiplier circuit, it can be shown thatthe output current Io is expressed as:
highisand lowisif  lowisand highisif 
 I  I  I  I  I 
bbo
4321432121
))2(tanh())2(tanh(
 
(12)
 
where
nU 
1
, with
n
is a slope factor ( in practice itlies between 1 and 2 and is close to 1 for high values of gatevoltage), and
 
is the thermal voltage whose value is 26mv atroom temperature. Current switching logic controlled by V
3
 and V
4
enables the output to change sign. The transfercharacteristic of the multiplier circuit is shown in figure 4. Itis noted that the output transfer characteristic is linearlyproportional to one of the multiplier inputs, I
b
, and variesnonlinearly with the other input, (V
1
-V
2
).
Figure 4. Transfer characteristic of the proposed four quadrant multiplier.
B. Complete CNN CMOS ImplementationFig. 5 shows a complete implementation of a CNN cell usingthe proposed multiplier circuit.
Io,u1Vu1VcomIb,u1IMr CVxVddV4,u1V3,u1VcomIo,u2Vu2VcomIb,u2V4,u2V3,u2VcomIo,y2Vy2VcomIb,y2V4,y2V3,y2VcomIo,y1Vy1VcomIb,y1V4,y1V3,y1VcomVunVyn
Cells’ inputs
u
(Nr)
Cells’ outputs
y
(Nr)
 
Figure5. Complete CNN cell.
V1V2IoIbV3 V4
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 9, No. 5, May 201145http://sites.google.com/site/ijcsis/ISSN 1947-5500

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