Computer System Architecture Memory Part I Chalermek Intanagonwiwat Slides courtesy of David Patterson Who Cares About the Memory Hierarchy? Processor-DRAM Memory Gap (latency) ebvkiins sole og we — Go Proc 000 | g f “Moore's Law’ eye £400 lProcessor enary 5 Performaice Gap’ 5 10 (grows 50 50% / f year) 3 .— tolis cevads ch cenmry aS bineN stalled mametoner ivetruction sye_weetany off ih Maton _ KRISTY, a rruv] T yr ad Trends je, ua. Capacity Speed (latency) Som 3495 Logic: 2x in 3years 2x in3 years wn DRAM: 4x in 3years 2x in 10 years I al Disk: 4x in 3 years 2x in 10 years ) ie wie + dine duiinhy DRA Year gggery S88 — pyr tse Tie | e000 fey 2 pe ng 1983 256 Kb / 220 ns 1986 1m 190 ns 1908 4m 165 ne 1992 16 m> \_ 145 ns ve Nam Sint | anes {ooo iy detecusfartsmd 2 oth Impact on Performance + Suppose a processor executes at sts ~Clock Rate = 200 MHz Gi bed (ns per cycle) ra i -OPE= 11 Et 50% arith/logic, 30% ld/st, 20% control + Suppose that 10% of memory operations get 50 cycle miss penaltySirinas etiss A dato memory slilaldnwa ess A. instruction meeoy Impact on Performance (cont.) + CPL = ideal CPI + average stalls per instruction = Licye) +( 0.30 (datamops/ins) x 0.10 (miss/datamop) x 50 (cycle/miss) ) = Li cycle+ 1.5 cycle 6 +58 % of the time the processor is stalled waiting for memory! a 1% instruction miss rate would add an additional 0.5 cycles to the CPI! attr An Expanded View of the « Memory System ~~ om” bechug Aope — — 3 Speed: Fastest mt Stomest Sor Sem eo @ The Goal: illusion of large, fast, Scheap memory 0999 -uiuis Fact: Large memories are slow, fast memories are small-‘wion How do we create a memory that is large, cheap and fast (most of the time)? asdel (= Hierarchy sitcona| - Parallelism Workin eteduvie F odateTle Why hierarchy works Phiemiamdstin ovens hues inththiterohelinge + The Principle of Locality: ~ Program access a relatively small portion of the address space at any instant of time. Aucochehugie— Sd use TS code Beef a i \ay renter Fi tain lutea a, Probabili of referehceJ pen meneny ees AP Fo Memory Hierarchy: How Does it Memory Hierarchy: Terminology Work? ‘ , : Hie ey + Hit: data appears in some block in the ie * Temporal Locality (Locality in Time): upper levei (example: Block X) | = i nical ee accessed data items - Hit Rate: the fraction of memory access er er mer oaniae found in the upper level * Spatial Locality (Locality in Space): ~ HiteTime: Time to access the upper level | => Move blocks consists of contiguous words which consists of to the upper levels. sles tuFubladsidua ex ere omy ofr vit tive = RAM access time + Time to determine hit/miss. Aslonseaie eae Terror [Piper Leet Memory | 2 103,803 Topmesnor_ [Terie] — | Memory fom troccsor | my romrocor | i Memory Hierarchy: Terminology Memory Hierarchy of a Modern (cont.) Computer System + Miss: data needs to be retrieve froma user fear mreerery mined wean? conerainis — | block in the lower level (Block Y) + By taking advantage of the principle of ° | - Miss Rate = 1- (Hit Rate) locality: | ~ Miss Penalty: Time to replace a block in the ~ Present the user with as much memory as is upper level + available in the cheapest technology. Time to deliver the block the pracessor + Hit Time <<)Miss Penalty ae Taner Level Betrmcenor [Upper tee ‘emery Memory - Provide access at the speed offered by the fastest technology. audrey sux From Procesor