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Computer System Architecture Processor Part III Chalermek Intanagonwiwat Slides courtesy of John Hennessy ond David Patterson (pn inten Tae a inqlemodin ft What's wrong with our CPI=1 processor? [Reg File Toul ALU Tood Load [ec [institemony [Rea Fie [oof _ALU [Data Mem Teo] Critical Path fast memories are small (large memories are slow) Bula memory oociuvemigsds + next Memory Access Time (cont.) + => Use a hierarchy of memories vel | entrain, winagnbile hank Garonne ee g toeley Processor—oaer=] 8 ! levee 23 ete 20-S0qees Basic Limits on Cycle Time + Next address logic - PC <= branch ? PC + of fset : PC +4 + Instruction Fetch - InstructionReg <= Mem[PC] + Register Access - Ac Rirs] + ALU operation ~ReArB Reducing Cycle Time + Cut combinational dependency graph and insert register / latch + Do same work in two fast cycles, rather than one slow one i slement (8) Scioscia Erstragecenent —] >" Basic Limits on Cycle Time (cont.) FC P g |; Logical Register Transfers + Physical — nino Register ‘000 PRE Ria B= RAT Step 2: Components of the Datapath ithaeu veg v9 ceu < senFary Transfers Step 3: RTL + Components => Datapath _ Step 4: Datapath + Logical RTs => Physical 2 RTS seynter deachirhs du vege, 6-5, fee AuimnartHt Legicnt | Regisher Sie eoedealnateauetu reqipee Bien be Step 5: Physical RTs => Control —semeenery pote “exec” swine:

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