Computer System Architecture
Processor Part III
Chalermek Intanagonwiwat
Slides courtesy of John Hennessy ond David Patterson
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What's wrong with our CPI=1
processor?
[Reg File Toul ALU Tood
Load
[ec [institemony [Rea Fie [oof _ALU [Data Mem Teo]
Critical Path fast memories are small
(large memories are slow)
Bula memory oociuvemigsds + nextMemory Access Time (cont.)
+ => Use a hierarchy of memories
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Processor—oaer=] 8
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Basic Limits on Cycle Time
+ Next address logic
- PC <= branch ? PC + of fset : PC +4
+ Instruction Fetch
- InstructionReg <= Mem[PC]
+ Register Access
- Ac Rirs]
+ ALU operation
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Reducing Cycle Time
+ Cut combinational dependency graph and
insert register / latch
+ Do same work in two fast cycles, rather
than one slow one i slement
(8)
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Basic Limits on Cycle Time (cont.)
FC
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Logical Register Transfers + Physical — nino
Register ‘000 PRE Ria B= RAT
Step 2: Components of the Datapath
ithaeu veg v9 ceu < senFary Transfers
Step 3: RTL + Components => Datapath _
Step 4: Datapath + Logical RTs => Physical 2
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Step 5: Physical RTs => Control —semeenery pote
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