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Application Notes

Application Notes

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Published by: elfrich on Jun 09, 2011
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02/13/2013

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Active-HDL
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 © 
Aldec, Inc.
Application Notes
 
i
Table Of Contents
Starting Active-HDL......................................................................................................................... 1Design Entry Overview.................................................................................................................. 15Design Management Overview ..................................................................................................... 27Handling Libraries in VHDL, Verilog, and EDIF............................................................................. 37Simulator Overview........................................................................................................................ 45BASIC Scripting Capabilities......................................................................................................... 54Tcl/Tk Scripting.............................................................................................................................. 61Creating FPGA and CPLD Designs............................................................................................... 71How to Simulate Designs .............................................................................................................. 77Using Stimulators........................................................................................................................... 85VHDL Testbench ........................................................................................................................... 91Glitches and Delta Cycle Handling................................................................................................ 99VHDL Debugging......................................................................................................................... 107Building and Debugging Handel-C Projects................................................................................ 115Co-simulation of Handel-C Projects in Active-HDL..................................................................... 125Using Celoxica Flowchart............................................................................................................ 133Using TestBencher Pro
with Active-HDL
............................................................................. 141Building PLI Applications............................................................................................................. 149Building VHPI Applications.......................................................................................................... 157Debugging C/C++ Applications ................................................................................................... 167Using Design Profiler................................................................................................................... 175Using Toggle Coverage............................................................................................................... 179Co-simulating VHDL and System-C............................................................................................ 183Co-simulating Verilog and System-C........................................................................................... 187Index............................................................................................................................................ 191

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