LN11 System Design Methodology

Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley
11-1
Objectives
After completing this chapter, you will be able to: Describe the features of finite-state machines (FSMs) Understand how to model FSMs Describe basic structures of register-transfer designs Describe basic structures and features of algorithmic-state machine (ASM) charts Understand how to model ASMs Describe the features and structures of datapath and control designs Describe the realizations of RTL designs Understand the relationship between iterative logic and FSMs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 11-2
Finite-State Machines (FSMs)

A finite-state machine (FSM) M is a quintuple M = (I, O, S, H, P) where I, O, and S are finite, nonempty sets of inputs, outputs, and states, respectively. H- v S p S is the state transition function; Pis the output function such that P: I v S p O for Mealy machine; P: S p O for Moore machine. The design issues of a finite-state machine used in digital systems are to compute both the state transition and output functions from inputs and (present) states.
Types of Sequential Circuits

Next state Inputs Combinational circuit D Q D QQ D CK CK CK Q' Q' Q' Clock Present state Combinational circuit
utputs
Moore machine
Next state
Inputs
Combinational circuit
D Q D QQ D CK CK CK Q' Q' Q' Clock
Combinational circuit
utputs
Present state
Mealy machine
11-4
State Encoding
Common FSM encoding options: One-hot code Binary code Gray code Random code Binary State
A B C D 00 01 10 11
Gray 00 01 11 10
One hot 1000 0100 0010 0001
One-hot encoding is usually used in F GA-based design, because there are a lot of registers in theses devices.
How to Realize an FSM?

Explicit fsm: States are declared explicitly. It is so easy to write clearly and correctly. Every synthesis tool supports this type FSM. Almost all FSMs are written in this type. Implicit fsm: States are not declared explicitly. The synthesis tools infer the state from the activity within a cyclic (always ) behavior. It is so hard to write clearly and correctly. ot every synthesis tool supports this type FSM.
11-6
(Explicit) FSM Realization

An explicit fsm is usually called FSM for short. Two major realization issues:
state-register declaration and update the computation of both next-state and output functions
State register can be declared as one register: harder to follow and model. two registers: easier to follow and model. Output and next state functions: continuous assignment function always block a combination of the above
FSM Modeling Styles

Style 1: one state register part 1: initialize and update the state register
always @(posedge clk or negedge reset_n) if (!reset_n) state <= A; else state <= next_state (state, x) ;
part 2: determine next state using function

function next_state (input present_state, x) case (present_state ) endcase endfunction
part 3: determine output function

always @(state or x) case (state) or assignment statements
FSM Modeling Styles

Style 2: two state registers part 1: initialize and update the state register
always @(posedge clk or negedge reset_n) if (!reset_n) present_state <= A; else present_state <= next_state;
part 2: determine next state

always @(present_state or x) case (present_state ) or assignment statements
part 3: determine output function

An FSM Example --- A 0101 Sequence Detector

Design a finite-state machine to detect the pattern 0101 in the input sequence x. Assume that overlapping pattern is 1/0 allowed.
Input (x) clock (clk) equence detector utput (z)
0/0 A 0/0 1/0 B 1/0 0/0 C 0/0 1/1 D
Block diagram Timing chart

t0 lock Input utput 0 0 1 0 0 0 1 1 0 0 0 0 t1 t2 t3 t4 t5
tate diagram
t6 t7 t8 t9 t10 t11
1 0
0 0
1 1
0 0
1 1
0 0
11-10
An FSM Example --- The Sequence Detector: Style 1a

// a behavioral description of 0101 sequence detector style 1a // Mealy machine example --- Using only state register and one always block. module sequence_detector_mealy (clk, reset_n, x, z); input x, clk, reset_n; output wire z; reg [1:0] state; // Use for both ps and ns parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // the body of sequence detector --- Using only one always block. always @(posedge clk or negedge reset_n) begin if (!reset_n) state <= A; else state <= fsm_next_state(state, x); end function [1:0] fsm_next_state (input [1:0] present_state, input x); reg [1:0] next_state; begin case (present_state) A: if (x) next_state = A; else next_state = B; B: if (x) next_state = C; else next_state = B; C: if (x) next_state = A; else next_state = D; D: if (x) next_state = C; else next_state = B; endcase fsm_next_state = next_state; end endfunction assign z = (x == 1 && state == D); endmodule
[0] [1]
un1_x_3 fsm_next_state_0.un12_state
un1_un12_state
e d e d e d e d e d e d
[0]
[0]
un1_x_2
D[1:0] R
Q[1:0]
[1:0]
[1]
state[1:0]
[0]
state_3[1]
un1_state_1
reset_n clk x
[0] [1]
un1_x_4 fsm_next_state_0.un18_state
un1_x
un1_un18_state
11-11
An FSM Example --- The Sequence Detector: style 1b

// a b ehavioral description of 0101 sequence detector: style 1b // Mealy machine example --- Using only one state register and two always blocks. module sequence_detector_mealy (clk, reset_n, x, z); input x, clk, reset_n; output reg z; // Local declaration reg [1:0] state; // Use for both ps and ns parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // the body of sequence detector --- Using two always blocks. always @(posedge clk or negedge reset_n) begin if (!reset_n) state <= A; else state <= fsm_next_state(state, x); end function [1:0] fsm_next_state (input [1:0] present_state, input x); . Same as that of style 1a end endfunction // evaluate output function z always @(state or x) case (state) A: if (x) z = 1'b0; else z = 1'b0; B: if (x) z = 1'b0; else z = 1'b0; C: if (x) z = 1'b0; else z = 1'b0; D: if (x) z = 1'b1; else z = 1'b0; endcase endmodule
An FSM Example --- The Sequence Detector: style 2
// a behavioral description of 0101 sequence detector: style 2 // Mealy machine example --- using two state registers and three always blocks. module sequence_detector_mealy (clk, reset_n, x, z); input x, clk, reset_n; output z; // local declaration reg [1:0] present_state, next_state; // present state and next state reg z; parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // initialize to state A and update state register always @(posedge clk or negedge reset_n) if (!reset_n) present_state <= A; // update present state else present_state <= next_state;
11-13
An FSM Example --- The Sequence Detector: style 2

// determine next state always @(present_state or x) case (present_state) A: if (x) next_state = A; else next_state = B; B: if (x) next_state = C; else next_state = B; C: if (x) next_state = A; else next_state = D; D: if (x) next_state = C; else next_state = B; endcase // evaluate output function z always @(present_state or x) case (present_state) A: if (x) z = 1'b0; else z = 1'b0; B: if (x) z = 1'b0; else z = 1'b0; C: if (x) z = 1'b0; else z = 1'b0; D: if (x) z = 1'b1; else z = 1'b0; endcase endmodule
clk
[ ] [ ]
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[ : ]
t st t [ ]
pr s
t st t
r s t
pr s
t st t [ : ]

pr s
t st t
[ : ]
[ : ]

pr s
t st t
pr s
t st t
[ ]
[ ] [ ]

pr s t st t
z

"
!
11-14
An FSM Example --- The Sequence Detector

Both modeling styles, using one state register or two state registers, yield the same circuit as shown below.
st t chi
E GFE
RTL result
clk r s t
I C
[ ]
Gate-level result
IBUF
% $ $%
pr s
t st t [
LUT
I O
Use Synplify with FSM compiler option.

LUT F C
A
C CL
ib f
F C
clk I O
z ob f
$
r s t
INV
I O
r s t c i r s t ib f
$ $ $ 6 # #
Although we declare two state registers, the synthesis tool only yields one state register.
11-15
IBUF
pr s
t st t
h.pr s
$ $ % $ #3 4# # (543 )
#3
4# #
$ %$ ) )
pr s
t st t
h.pr s
t st t [ ]
t s t t [ ]z
)#3
4# #
#3
4# #
clk i b f
$
[ ]
[ ]
[ ]
C CL
[ ]
BUFGP
6
[ ]
[ ]
$ )2 '
$ $
LUT
9 7
L C
'
$ $
& # # 6 $ & CC
c i OBUF
Coding Style
State name should be described using parameters: parameter or localparam. Combinational logic for computing the next state should be separated from the state registers, i.e., using its own always block or a function. The combinational logic of next state function should be implemented with a case statement.
11-16
Explicit vs. Implicit FSMs
// an implicit FSM example module sum_3data_implicit(clk, data, total); parameter = 8; input clk; input [ -1:0] data; un1[2:0] output [ -1:0] total; t tal[7:0] t tal_9[7:0] reg [ -1:0] total; + // we do not declare state registers. un1_t tal[7:0] always begin Both implicit and explicit fsm @(posedge clk) total <= data; have the same synthesized results. @(posedge clk) total <= total + data; @(posedge clk) total <= total + data; end endmodule
clk
[1:0] [2]
D[2:0]
Q[2:0]
[2:0]
[0]
[7:0] [7:0]
0 1
[7:0]
[7:0]
data[7:0]
[7:0]
[7:0] [7:0]
[7:0]
D[7:0]
H
Q[7:0]
[7:0] [7:0]
t tal[7:0]
11-17
Explicit vs. Implicit FSMs

// an explicit FSM example module sum_3data_explicit(clk, reset, data, total); st t chi parameter = 8; input clk, reset; st t [ : ] input [ -1:0] data; tot l [ : ] tot l[ : ] output [ -1:0] total; reg [ -1:0] total; tot l[ : ] reg [1:0] state; // declare state registers explicitly parameter A = 2'b00, B =2'b01, C = 2'b10; always @(posedge clk) Both implicit and explicit fsm if (reset) state <= A; else have the same synthesized results. case (state) A: begin total <= data; state <= B; end B: begin total <= total + data; state <= C; end C: begin total <= total + data; state <= A; end endcase endmodule
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dh
t [ : ]
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UY P
U Y `XP
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i q
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tot l[ : ]
11-18
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dh dh
dh
dh
[ : ]
dh dh
dc
UTQP
UY P
XWSV
r s t clk
I C
QS
PRQ P
dh
dh
dh
s s a
i qq
Register-Transfer-Level Design
Features of register-transfer-level (RTL) designs are sequential machines. are structural. concentrate on functionality, not details of logic design. Two types of register-transfer-level design are ASM (algorithmic-state machine) chart Datapath and controller
11-19
ASM Charts
ASM (algorithmic state machine) charts specify RTL operations on the per-cycle basis. show clearly the flow of control from state to state. are very suitable for data path-controller architectures. An ASM chart is composed of State block Decision block Conditional output block
11-20
ASM State Blocks

A state block specifies a machine state and a set of unconditional RTL operations associated with the state. may execute as many actions as you want and all actions in a state block occur in parallel. occupies a clock period along with its related operations.
State name State assignment
Output/operations
11-21
Decision Blocks
A decision block describes the condition under which ASM will execute specific actions. selects the next state based on the value of primary input or present state. can be drawn in either two-way selection or multi-way selection.
Two-way selection
(invalid) 0 (Valid) 1
Multi-way selection
ondition (invalid) 0 (Valid) 1
ondition
ondition
11-22
Conditional Output Blocks

A conditional output block describes the RTL operations executed under conditions specified by one or more decision blocks. receives signals from the output of a decision block or the other conditional output block. can only evaluate present state or primary input value on present cycle.
utput/operation
11-23
ASM Blocks
An ASM block has exactly one entrance path and one or more exit paths.
A 00 B n B+3 0 cn 0 1 d n 5 0 1 x2 x1
A 00 B n B+3
0 1 c n 0
x1 d n 5
1 0
x2
Serial testing
arallel testing
11-24
ASM Charts --- ASM Blocks

ASM blocks An ASM block contains one state block and a serialparallel network of decision blocks and conditional output blocks. Each ASM block describes the operations executed in one state. The basic rules for constructing an ASM chart Each state and its associated set of conditions must define a unique next state. Every path of the network of conditions must terminate at a next state. There cannot exist any loop in the network of conditions.
Invalid ASM Blocks

Undefined next state: why? Try to explain it!
A 00 B n B+3
x1
x2
c n 0 C
d n 5
10
01
A 00 B n B+3 1 c n 0 1 C x2 0
Undefined exit path: why? Try to explain it!
x1 0 10 B
d n 5 01
11-26
ASM Modeling Styles

Style 1a: one state register and one always block. ( ot a good style!!!) part 1: initialize, determine, update the state register, and determine RTL operations. always @(posedge clk or negedge start_n) if (!start_n) state <= A; else state <= ; Style 1b: one state register and two always blocks part 1: initialize, determine, and update the state register. always @(posedge clk or negedge start_n) if (!start_n) state <= A; else state <= ; part2: determine RTL operations always @(posedge clk) case (state ) or assignment statements
ASM Modeling Styles

Style 2: two state registers and three always blocks (the best style !!!!) part 1: initialize and update the state register
always @(posedge clk or negedge start_n) if (!start_n) present_state <= A; else present_state <= next_state;
part 2: determine next state

part 3: determine RTL operations

always @(posedge clk) case (present_state ) Or assignment statements
An ASM Example --- Booth Multiplier

Problem Specification: Booth multiplication algorithm
Assume that: X ! xn1 xn2 . x1 x0 Y ! yn 1 yn 2 . y1 y0
At ith step:
Add 0 to partial product P if xi xi 1 ! 00 Add Y to partial product P if xi xi 1 ! 01 Subtract Y from partial product P if xi xi 1 ! 10 Add 0 to partial product P if xi xi 1 ! 11
11-29

acc mp 77 mcand 13 00000000 - 00010011 1 1 1 1 + 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 mp mp(0) 0 cnt 7 acc acc - mcand 01110111
10111011 01011101 10101110
1 1 1
7 6 5
right shi right shi right shi acc
t acc:mp t acc:mp t acc:mp acc +mcand
00010000 00001000 - 00010011 1 1 1 1 + 0 08 5 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 0 1
01010111
right shi t acc:mp
10101011 01010101 10101010
1 1 1
3 2 1
right shi right shi right shi acc
t acc:mp t acc:mp t acc:mp acc +mcand
00010001 00001000
11010101
right shi t acc:mp

11-30

ASM chart approach
idle compute
1 inish load mcand mp acc cnt 0 multiplicand multiplier 0 -1 acc
01
mp[1:0] 00 11
10
acc + mcand
acc
acc - mcand
shift_right {acc, mp} cnt {acc[n-1], acc, mp} cnt - 1 0 1 cnt ! 0
finish
11-31
An ASM Example --- Booth Multiplier: Style 2 (1/3)

// Booth multiplier: style 2 --- using three always blocks module booth (clk, start_n, multiplier, multiplicand, product, finish); parameter W = 8; // word size parameter = 3; // = log2(W) input clk, start_n; input [W-1:0] multiplier, multiplicand; output [2*W-1:0] product; wire [2*W-1:0] product; reg [W-1:0] mcand, acc; reg [ -1:0] cnt; reg [W:0] mp; // one extra bit reg [1:0] ps, ns; output reg finish; // finish flag parameter idle = 2'b00, load = 2'b01, compute = 2'b10, shift_right = 2'b11; // the body of the w-bit booth multiplier // initialize to state idle always @(posedge clk or negedge start_n) if (!start_n) ps <= idle; else ps <= ns;

// determine next state always @(*) case (ps) idle: if (!finish) ns = load; else ns = idle; load: ns = compute; compute: ns = shiftright; shiftright: if (cnt == 0) ns = idle; else ns = compute; endcase // execute RTL operations always @(posedge clk) begin if (!start_n) finish <= 0; case (ps) idle: ; load: begin mp <= {multiplier,1'b0}; mcand <= multiplicand; acc <= 0; cnt <= W - 1; end

compute: begin case (mp[1:0]) 2'b01: acc <= acc + mcand; 2'b10: acc <= acc - mcand; default: ; // do nothing endcase end shift_right: begin {acc, mp} <= {acc[W-1], acc, mp[W:1]}; cnt <= cnt - 1; if (cnt == 0) finish <= 1; end endcase end assign product = {acc, mp[W:1]}; endmodule
11-34
An ASM Example ---Booth Multiplier

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pro
ltiplic
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cc 5
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cc
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fi ish
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fi ish
st t [ : ]
st t
fi ish
st t [ ]
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cc 6
cc 5
st rt
st t
c t[ : ]
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st t
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ug
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i ie
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st t
chi
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I[ : ] C
ltipli r[ : ] clk
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cc[ : ]
wt t
i y x y
g f w u
ug
c t 5[ : ]
cc 5
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[ : ] [ : ] =
[ : ]
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cc[ : ]
p 5[ : ]
p[ : ]
uv
h h e
uv
uv
y u w
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d de
c t[ : ]
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u ut wv u
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g ut f vu w
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wv ut
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y x ut ut
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d de y x
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uuuw w w ww ug ug ug w
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d jm m
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11-35
dp+cu Architecture Design

A digital system can be considered as a system composed of three major parts: data path performs all operations that are required in the system. Memory temporarily stores the data used and generated by data path unit. control unit controls and schedules all operations performed by the data path unit.
Memory ead/ rite
n p n
ata
n
ata input
clk
ontroller
ontrol signals
o q n
atapath
ata output
tatus
11-36
A dp+cu Approach Example --- Booth Multiplier

Datapath and controller units can be easily derived from ASM chart (ASM modeling style 2). Datapath part corresponds to the registers and function units in RTL operation block (part 3). Controller corresponds to the first and second always blocks (part 1 and 2), which determines the next state function, and the control signals in the RTL operation block (part 3).
11-37
A dp+cu Approach Example --- Booth Multiplier
mcand mcand_qout add_sub 3
start_n mcand_load
start_n inish ontrol unit
add_sub
sum_out start_n 3 acc_mode acc acc_qout[ -1]
start_n mp_mode mp
mp[1:0]
acc_rso acc_qout
11-38
A Three-Step Paradigm
1. Model the design (usually described by an ASM chart) using any modeling style described above as a single module. 2. Extract the datapath from the module and construct it as an independent module. 3. Extract control-unit module and construct top module. Add a top module that instantiates both datapath and control-unit
11-39
Realization Options of RTL Design

The rationale behind these options is a tradeoff among performance (throughput, operating frequency), space (area, hardware cost), and power consumption. Single cycle uses combinational logic only to realize the required functions. It may require a quite long propagation time to finish a computation of required functions.
D C
11-40

Multiple cycle executes the required functions in consecutive clock cycles. Linear structure performs straightforward the required functions without sharing resources.
D Q CK D Q CK D Q CK
11-41

Nonlinear (feedback or feed-forward) structure performs the required functions with sharing resources by using feedback or feed-forward connection.
D C
Single-stage nonlinear structure
D C
D C
D C
Multiple-stage nonlinear structure


Pipeline is also a multiple cycle structure in which a new data can be fed into the structure at each clock cycle. Hence, it may output a result per clock cycle after the pipeline is fully filled.
Input D Q CK clk D Q CK D Q CK utput
11-43
A Single-Cycle Example
// a single-cycle example module single_cycle_example(clk, data_a, data_b, data_c, total); parameter N = 8; input clk; input [N-1:0] data_a, data_b, data_c; output reg [N-1:0] total; // compute total = data_c - (data_a + data_b) always @(posedge clk) begin total <= data_c - (data_a + data_b); end endmodule
clk data_c[7:0] data_a[7:0] data_ [7:0]
t
[7:0] [7:0] [7:0]
[7:0] [7:0] [7:0]

s
+
un2_t tal[7:0]
[7:0]
[7:0] 1
+
t tal_1[7:0]
[7:0]
[7:0]
D[7:0]
Q[7:0]
[7:0]
[7:0]
t tal[7:0]
t tal[7:0]
11-44
A Multiple-Cycle Example
// a multiple cycle example --- an implicit FSM module multiple_cycle_example(clk, data_a, data_b, data_c, total); parameter N = 8; input clk; input [N-1:0] data_a, data_b, data_c; output reg [N-1:0] total; reg [N-1:0] qout_a, qout_b; // compute total = data_c - (data_a + data_b) always @(posedge clk) begin qout_a <= data_a; @(posedge clk) qout_b <= qout_a + data_b; @(posedge clk) total <= data_c - qout_b; end endmodule
t c[ : ] t b[ : ] t [ : ]
[ : ] [ : ] [ : ] [ : ] [ : ]
clk
{ ~ }|x
[ : ]
qo t
[ : ]
{~ }
{ ~ |}
{~
|x
{ ~ | |x
{ z zyx
[ : ]
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qo t b
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qo t b[ : ]
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tot l
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tot l[ : ]
11-45
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w v
v v
vw
w u v
v v v
Pipeline Principles
Pipelining: a pipeline is composed of several stages with each stage consisting of a combinational logic circuit and a register, called pipeline register. Pipeline latency: the number of cycles between the presentation of an input value and the appearance of its associated output.
clock period
latency
2 3 4 5 Pipeline depth
11-46
Pipelined Systems
The pipelined clock fpipe is set by the slowest stage and is larger than the frequency used in the original cascaded system.
Input register Input register Input register Input register
Logic
Logic
Logic
Input
Logic
Output
clk
For the ith-stage, the smallest allowable clock period Ti is determined by the following condition:
i
The pipelined clock period for an m-stage pipeline is chosen to be: pipe ! max{ i | i ! 1, 2, ..., m}
"t
t setup t d ,i t skew ,i 1
A Simple Pipeline Example --- Not a Good One

// a simple pipeline example --- Not a good one module simple_pipeline(clk, data_a, data_b, data_c, total); parameter N = 8; input clk; input [N-1:0] data_a, data_b, data_c; output reg [N-1:0] total; reg [N-1:0] qout_a, qout_b; // compute total = data_c - (data_a + data_b) always @(posedge clk) begin qout_a <= data_a; qout_b <= qout_a + data_b; total <= data_c - qout_b; end endmodule
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qo t b
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qo t b[ : ]
qo t
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tot l[ : ] tot l [ : ]
clk [ : ]
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11-48
A Simple Pipeline Example

// a simple pipeline example module pipeline_example(clk, data_a, data_b, data_c, total); parameter N = 8; input clk; input [N-1:0] data_a, data_b, data_c; output reg [N-1:0] total; reg [N-1:0] qout_a, qout_b, qout_c, qout_d, qout_e; // compute total = data_c - (data_a + data_b) always @(posedge clk) begin qout_a <= data_a; qout_b <= data_b; qout_c <= data_c; qout_d <= qout_a + qout_b; qout_e <= qout_c; total <= qout_e - qout_d; end endmodule
data_c[7:0]
[7:0]
t tal_1[7:0]
t tal[7:0]
[7:0] [7:0] [7:0] [7:0] [7:0]
ut_a[7:0]
ut_d_1[7:0]
data_a[7:0]
D[7:0] Q[7:0]
[7:0]
[7:0]
D[7:0] Q[7:0]
[7:0]
ut_d[7:0]
ut_ [7:0]
11-49
ut_c[7:0]
clk data_ [7:0]
[7:0]
[7:0]
[7:0]
D[7:0] Q[7:0]
[7:0]
D[7:0] Q[7:0]
[7:0]
[7:0]
D[7:0] Q[7:0]
[7:0]
[7:0] [7:0]
ut_e[7:0]
[7:0]
[7:0]
D[7:0] Q[7:0]
[7:0] [7:0]
t tal[7:0]
FSM vs. Iterative Logic

An iterative logic can be considered as an FSM expansion in time. At each time step, the combinational logic part of the FSM is duplicated and the memory element part is ignored.
x[i] x ombinational logic ps ns z ps[i] Combinational logic z[i] ns[i]
s s
An example of 1-D iterative logic

x[0] ns[0] Comb. logic ps[0] z[0] ps[1] z[1] Comb. logic ps[2] ps[i] z[i] x[1] ns[1] Comb. logic x[i]
A nonlinear structure may be transferred into a linear one.

ns[i] x[n-1] x[n-2] ns[i] ns[n-1] Comb. Comb. logic logic ps[n-2] ps[n-1] z[n-1] z[n-2]
ps[i+1]
11-50
An Example of Iterative Logic --- A Sequence Detector

xi PS A yi1 yi2 zi ith stage Yi1 Yi2 B C D xi NS, zi 0 B,0 B,0 D,0 B,0 1 A,0 C,0 A,0 C,1 xi Yi1 Yi2 0 1 01 01 11 01 00 10 00 10 xi zi
yi1 yi2 00 01 10 11
0 0 0 0 0
1 0 0 0 1
xi
yi1yi2 00
0
01
2
11
6
10
4
xi
yi1yi2 00
0
01
2
11
6
10
4
xi
yi1yi2 00
0
01
2
11
6
10
4
0 1
0
1
0
3
0
7
1
5
0 1
1
1
1
3
1
7
1
5
0 1
0
1
0
3
0
7
0
5
0 Yi1
0 Yi2
0 x'i
0 zi
1 xiyi1yi2
xiyi2 + x iyi1y i2
11-51

xi
1/0 0/0 A 1/0 0/0 B 1/0 C 0/0 0/0 1/1 D
yi1 Yi1 yi2 Yi2
State diagram
zi
0 x1 0
1 x2
0 x3 1
1 x4
0 x5
1 x6
0 0
y11
1 1 y12 z Y12 1 0
Y11
y21 y22
Y21 1 2 0 z2 Y22 0
y31
3 1 y32 z Y32 3 0
Y31
y41 y42
Y41 1 4 0 z4 Y42 1
y51 y52
Y51 1 5 1 z5 Y52 0
y61 y62
Y61 1 6 0 z6 Y62 1
11-52

// Behavioral description of 0101 sequence detector --- An iterative logic version. module sequence_detector_iterative (x, z); parameter n = 6; // define the size of 0101 sequence detector input [n-1:0] x; output wire [n-1:0] z; // Local declaration. wire [n-1:0] next_state_1, next_state_0 ; parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // Using generate block to produce an n-bit 0101 sequence detector. genvar i; generate for(i = 0; i < n; i = i + 1) begin: detector_0101 if (i == 0)begin: LSB // describe LSB cell basic_cell bc (x[i], A, z[i], {next_state_1[i], next_state_0[i]}); end else begin: rest_bits // describe the rest bits basic_cell bc (x[i], {next_state_1[i-1], next_state_0[i-1]}, z[i], {next_state_1[i], next_state_0[i]}); end end endgenerate endmodule

// Determine next state using function next_state. module basic_cell (x, present_state, output_z, next_state); input x; input [1:0] present_state; output reg [1:0] next_state; output reg output_z; parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; // Determine the next state Exactly the same as the next always @(present_state or x) case (present_state) state logic of FSM. A: if (x) next_state = A; else next_state = B; endcase // Determine the output value Exactly the same as the output always @(present_state or x) case (present_state) logic of FSM. A: if (x) output_z = 1'b0; else output_z = 1'b0; endcase endmodule
An Example of 2D-Iterative Logic --- Booth Multiplier

xi 0 0 1 1 xi - 1 add_sub_sel add_sub_en 0 1 0 1
J 0 1 J
Operation Shift only Add and shift Subtract and shift Shift only
Pin
0 1 1 0
yi
add_sub_sel C RL xi-1 add_sub_en xi Cout FA CAS yi Pi Cin
add_sub_sel
add_sub_en
11-55
An Example of 2D-Iterative Logic --- Booth Multiplier

0 0 1
y3 0
y2 1
y1 1
0 1 CAS
y0
1 add_sub_sel C RL CAS 1 add_sub_en 1 1 0 1 0 CAS 0 0 1 0 0 CAS 1 0 1 1 0 CAS 0 P6 1 0 P5 CAS 0 0 P4 1 0 1 1 1 CAS 0 P3 CAS 1 1 1 0 1 CAS 0 CAS 1 1 0 CAS 1 0
x0
CAS 0 1 CAS 0 CAS 1 P2

0,3
CAS 0 1 CAS 0 1 P1 0
0,2
0 1 P0 0
0,1
0,0
x1
C RL 1
1 1 P7
x3
C RL
x2
C RL
C0,i
add_sub_sel add_sub_en
11-56

LN11 System Design Methodology

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Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Finite-State Machines (FSMs)

Chapter 11: System Design Methodology

Types of Sequential Circuits

D Q D QQ D CK CK CK Q' Q' Q' Clock

Chapter 11: System Design Methodology

One hot 1000 0100 0010 0001

Chapter 11: System Design Methodology

How to Realize an FSM?

Chapter 11: System Design Methodology

(Explicit) FSM Realization

Chapter 11: System Design Methodology

FSM Modeling Styles

 part 2: determine next state using function

 part 3: determine output function

Chapter 11: System Design Methodology

FSM Modeling Styles

 part 2: determine next state

 part 3: determine output function

Chapter 11: System Design Methodology

An FSM Example --- A 0101 Sequence Detector

Block diagram Timing chart

Chapter 11: System Design Methodology

An FSM Example --- The Sequence Detector: Style 1a

Chapter 11: System Design Methodology

An FSM Example --- The Sequence Detector: style 1b

Chapter 11: System Design Methodology

An FSM Example --- The Sequence Detector: style 2

Chapter 11: System Design Methodology

An FSM Example --- The Sequence Detector: style 2

Chapter 11: System Design Methodology

An FSM Example --- The Sequence Detector

Use Synplify with FSM compiler option.

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Explicit vs. Implicit FSMs

Chapter 11: System Design Methodology

Explicit vs. Implicit FSMs

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

ASM State Blocks

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Conditional Output Blocks

Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

ASM Charts --- ASM Blocks

Chapter 11: System Design Methodology

Invalid ASM Blocks

Undefined exit path: why? Try to explain it!

Chapter 11: System Design Methodology

ASM Modeling Styles

Chapter 11: System Design Methodology

ASM Modeling Styles

 part 2: determine next state

 part 3: determine RTL operations

Chapter 11: System Design Methodology

An ASM Example --- Booth Multiplier

part 2: determine next state using function

part 3: determine output function

part 2: determine next state

part 3: determine output function

part 2: determine next state

part 3: determine RTL operations

An example of 1-D iterative logic