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Table Of Contents

CHAPTER 1: Introduction
2.1 Theory and implementation of watermark algorithms
2.1.1 Watermark Classifications
Figure 2.1 General classification of existing watermarking algorithms
watermark
2.1.2 Watermark Design Considerations
2.1.2.1 Robustness to Attacks
2.1.2.2 Image quality
2.1.2.3 Computational complexity
2.1.3 Figures of Merit for Watermarking Systems
2.2 Watermark implementations – Software vs. Hardware
Figure 2.3 Scheme of general watermark system
2.3 State of the art in hardware watermarking
3.2.1 DCT based compression
Figure 3.2: Example quantization table given in the JPEG standard [4]
3.3.1 The novel watermark embedding algorithm
Figure 3.5: 8x8 Block DCT conversion and 1x64 Zigzag reordering
Figure 3.6: Reorganization of the DCT data in the Zigzag order
Figure 3.7: Example DCT data for blocks J3, J2
3.3.2 Implementation of the embedding module in HW
HW
3.4 Watermark generation
3.4.1 RNG based watermark generation
3.4.2 Existing RNG structures
3.4.2.1 The LFSR
Figure 3.9: A generalized Fibonacci implementation of an LFSR circuit
3.4.2.2 The FCSR
Figure 3.10: Galois implemented FCSR
3.4.2.3 The Filtered FCSR (F-FCSR)
3.4.3 RNG based watermark generator design method and implementation
Figure 3.11: A Gollman cascade RNG
CHAPTER 4: Implementation, testing and results
4.1 Software implementation and algorithm functionality verification
Figure 4.1: Algorithm Matlab© simulation results
4.2 Algorithm performance evaluation
4.2.1 Fragile watermarking and benchmarking
Figure 4.2: additional sample images
Table 4.1: N vs. Quantization-Level Tradeoffs
4.3 Hardware design and verification
Figure 4.3: Test setup schematic
4.3.1 Hardware Experimental Results
Table 4.2: FPGA Synthesis Results
4.4 Physical proof of concept implementation
Figure 4.5: A general implementation of an imaging system
Figure 4.6: Mixed signal SoC fast prototyping custom development board
4.4.1 The CMOS Image sensor
4.4.2 Digital signal processing and control
Figure 4.7: Internal structure of the FPGA digital design
Table 4.3: Resource utilization by modules in the overall design
Figure 4.8: Sample output image from the physically implemented system
4.4.3 Output image capture
CHAPTER 5: Conclusion
5.1 Thesis summary
5.2 Issues that still need attention and future work
5.3 Possible future directions for development
References
APPENDIX A: MATLAB CODE
A.1. Simulation Testbench and peripherals
A.1.1. Simulation Envelope
A.2. Compression/Decompression
A.3. Algorithm Implementation
A.3.1. Embedding
A.3.2. Detection
APPENDIX B: VERILOG CODE
B.1. Top Level and Peripheral Modules
B.2. CMOS Imager Control Logic and Interface
B.3. JPEG Encoding and Watermark Embedding
B.3.1. Watermark Embedding
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Published by Yassine Ahmed

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Published by: Yassine Ahmed on Jun 28, 2011
Copyright:Attribution Non-commercial

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07/10/2013

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