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Table Of Contents

1) Chapter One
Basic Assembly Language Programming Concepts
Binary Numbers
Grouping Bits into Bytes
Figure 1-1 Binary Representation
Figure 1-2 Bit Numbers
Hexadecimal Representation of Binary
Table 1-1 Decimal and Hex Numbers
Boolean Logic
Logical And
Table 1-2 Truth Table for AND
Logical Or
Figure 1-4 ORing Bits
Logical Exclusive Or
Table 1-3 Truth Table for OR
Figure 1-5 EXCLUSIVE ORing Bits
Table 1-4 Truth Table for EXCLUSIVE OR
Logical Complement
Figure 1-6 COMPLEMENTing Bits
Figure 1-7 COMPLEMENTing Bits Using Exclusive OR
Table 1-5 Truth Table for COMPLEMENT
Signed Numbers
Table 1-6 The Eight-Bit Range of Two’s-Complement Numbers
Storing Numbers in Decimal Form
Table 1-7 The First 16 BCD Numbers
Computer Arithmetic
Microprocessor Programming
Machine Language
Assembly Language
Writing in Assembly Language
Basic Programming Concepts
Selection Between Paths
2) Chapter Two
Architecture of the 6502
Microprocessor Architecture
The 6502 Registers
The Accumulator
The X and Y Index Registers
Table 2-1 Status Register Condition Code Flags
Table 2-2 Status Register Mode Select Flags
Figure 2-2 Initializing the Stack Pointer to $FF
Figure 2-3 After Pushing the Accumulator
The Program Counter
Addressing Modes
Table 2-3 6502 Addressing Modes
Figure 2-4 Indexing: Base Plus Index
The 6502 System Design
Memory Order of Multiple-Byte Values
Memory-Mapped Input/Output
NMOS Process
Bugs and Quirks
3) Chapter Three
Architecture of the 65C02
The 65C02 Architecture
Table 3-1 The 65C02’s New Addressing Modes
Table 3-2. New 65C02 Instructions
CMOS Process
4) Chapter Four
Sixteen-Bit Architecture The 65816 and the 65802
Power-On Status: 6502 Emulation Mode
The Full-Featured 65x Processor: The 65816 in Native Mode
Figure 4-1 65816 Native Mode Programming Model
The Program Bank Register
The Data Bank Register
The Direct Page Register
The Stack Pointer
Accumulator and Index Registers
Table 4-1 The Four Possible Native Mode Register Combinations
Switching Registers Between Eight and Sixteen Bits
The Status Register
Figure 4-2 Results of Switching Register Size
6502/65C02 Addressing Modes on the 65816
Table 4-2 Addressing Modes: Zero Page vs. Direct Page
New 65816 Addressing Modes
Table 4-3 The 65816/65802’s New Addressing Modes
Table 4-4 New 65816/65802 Instructions
Table 4-5 Interrupt Vector Locations
The 65802 Native Mode
Figure 4-3 65802 Native Mode Programming Model
Emulation Mode
Emulation Mode Registers
Switching Between 6502 Emulation and Native Modes
Switching from Emulation to Native Mode
Switching from Native to Emulation Mode
65802/65816 Bugs and Quirks
5) Chapter Five
SEP, REP, and Other Details
The Assembler Used in This Book
Address Notation
6) Chapter Six
First Examples: Moving Data
Pushing and Pulling the 65816’s Additional Registers
Pushing Effective Addresses
Other Attributes of Push and Pull
Moving Data Between Registers
Storing Zero to Memory
Block Moves
7) Chapter Seven
SimpleAddressing Modes
Table 7-1 List of Simple Addressing Modes
Immediate Addressing
Figure 7-1 Immediate Addressing: 8 vs. 16 bits
Absolute Addressing
Figure 7-2 Absolute Addressing
Direct Page Addressing
Figure 7-3 Zero Page Addressing
Figure 7-4 Indexing
Figure 7-5 Indexing Beyond the End of the Bank
Absolute Indexed with X and Absolute Indexed with Y Addressing
Figure 7-6 Absolute Indexing with a Generic Index Register
Direct Page Indexed with X and Direct Page Indexed with Y Addressing
Figure 7-7 Direct Page Indexing with a Generic Index Register
Accumulator Addressing
Implied Addressing
Direct Page Indirect Addressing
Figure 7-8 Direct Page Indirect Addressing
Absolute Long Addressing
Figure 7-9 Absolute Long Addressing
Absolute Long Indexed with X Addressing
Direct Page Indirect Long
Figure 7-10 Direct Page Indirect Long Addressing
Block Move
8) Chapter Eight
The Flow of Control
Table 8-1. Branch and Jump Instructions
Jump Instructions
Figure 8-1 Jump’s Absolute Indirect Addressing Mode
Conditional Branching
Figure 8-2. Relative Branch Calculation
Branching Based on the Zero Flag
Figure 8-3. Linked List
Branching Based on the Carry Flag
Branching Based on the Negative Flag
Branching Based on the Overflow Flag
Limitations of Conditional Branches
Unconditional Branching
9) Chapter Nine
Built-In Arithmetic Functions
Increment and Decrement
Table 9-2. Equalities
Signed Arithmetic
Signed Comparisons
Decimal Mode
Logic and Bit Manipulation Operations
Table 10-1 Logic Instructions
Logic Functions
Logical AND
Figure 10-1 The AND Operation
Logical OR
Logical Exclusive-Or
Bit Manipulation
Shifts and Rotates
Figure 10-2 Shift and Rotate Left
11) Chapter Eleven
The Complex Addressing Modes
Table 11-1 Complex Addressing Modes
Relocating the Direct Page
Assembler Addressing Mode Assumptions
Table 11-3 Assembler Syntax for Complete Memory Access
Direct Page Indirect Indexed With Y Addressing
Figure 11-1 Postindexing
Direct Page Indexing Indirect Addressing
Absolute Indexed Indirect Addressing
Figure 11-3 Absolute Indexed Indirect
Direct Page Indirect Long Indexed with Y Addressing
Stack Relative Addressing
Figure 11-5 Stack Relative
Stack Relative Indirect Indexed Addressing
Push Effective Instructions
Figure 11-6 Stack Relative Indirect Indexed
Return from Subroutine Long
Branch to Subroutine
Figure 12-4 RTL
Coding a Subroutine: How and When
6502 Eight-Bit Negation – A Library Example
65C02, 65802, and 65816 Eight-Bit Negation
6502 Sixteen-Bit Negation
65802 and 65816 Sixteen-Bit Negation
Parameter Passing
13) Chapter Thirteen
Interrupts and System Control Instructions
Table 13-1. Interrupt and System Control Instructions
Figure 13-1 I/O Management: Interrupts vs. Polling
Figure 13-2 Interrupt Processing
Table 13-2 Interrupt Vectors
Figure 13-3Break Signature Byte Illustration
Processing Interrupts
Figure 13-4 6522 VIA Interrupt Flag Register
Interrupt Response Time
Table 13-3 Reset Initialization
Status Register Control Instruction
No Operation Instructions
14) Chapter Fourteen
Selected Code Samples
6502 Multiplication
65C02 Multiplication
65802 and 65816 Multiplication
6502 Division
65C02 Division
65802/65816 Division
Calling an Arbitrary 6502 Routine
Figure 14-1 Stack Snapshot after PEI (12) Instruction
Testing Processor Type
Compiler-Generated 65816 Code for a RecursiveProgram
The Same Example Hand-Coded in Assembly Language
The Sieve of Eratosthenes Benchmark
15) Chapter Fifteen
DEGUG16 – A 65816 Programming Tool
Figure 15-1 Disassembly Output
Figure 15-2 Tracer Output
16) Chapter Sixteen
Design and Debugging
Debugging Checklist
Decimal Flag
Adjusting Carry Prior to Add / Subtract
65x Left-to-Right Syntax
65x Branches
6502 Jump Bug
Interrupt-Handling Code
65802/65816: Emulation Versus Native Mode
65802/65816: Eight-Bit Versus Sixteen-Bit Registers
65802/65816: The Direct Page
65802/65816: Stack Overruns Program or Data
65802/65816: JSR/JSL and RTS/RTL
65802/65816: MVN/MVP
Return Address
Inconsistent Assembler Syntax
Generic Bugs: They Can Happen Anywhere
Uninitialized Variables
Missing Code
Failure to Increment the Index in a Loop
Failure to Clean Up Stack
Immediate Data Versus Memory Location
Initializing the Stack Pointer from a Subroutine
Top-Down Design and Structured Programming
17) Chapter Seventeen
The Addressing Modes
Table 17-1 Operand Symbols
Absolute Indexed, X Addressing
Absolute Indexed, Y Addressing
Absolute Indirect Addressing
Absolute Indirect Long Addressing
Absolute Long Indexed, X Addressing
Block Move Addressing
Direct Page Indexed, X Addressing
Direct Page Indexed, Y Addressing
Direct Page Indexed Indirect, X Addressing
Direct Page Indirect Long Addressing
Direct Page Indirect Indexed, Y Addressing
Stack (Direct Page Indirect) Addressing
Stack (Interrupt) Addressing
Stack (Program Counter Relative) Addressing
Stack (Pull) Addressing
Stack (Push) Addressing
Stack (RTI) Addressing
Stack (RTL) Addressing
Stack (RTS) Addressing
Stack Relative Indirect Indexed, Y Addressing
18) Chapter Eighteen
The Instruction Sets
Table 18-1 Operand Symbols
And Accumulator with Memory AND
Figure 18-1 AND Truth Table
Shift Memory or Accumulator Left ASL
Figure 18-2 ASL
Branch if Carry Clear BCC
Branch if Carry Set BCS
Test Memory Bits against Accumulator BIT
Branch if Not Equal BNE
Software Break BRK
Branch Always Long BRL
Branch if Overflow Clear BVC
Branch if Overflow Set BVS
Clear Decimal Mode Flag CLD
Clear Interrupt Disable Flag CLI
Clear Overflow Flag CLV
Compare Accumulator with Memory CMP
Co-Processor Enable COP
Figure 18-4 Stack after COP
Compare Index Register X with Memory CPX
Compare Index Register Y with Memory CPY CPY
Decrement Index Register X DEX
Decrement Index Register Y DEY
Exclusive-OR Accumulator with Memory EOR
Figure 18-5Exclusive OR Truth Table
Increment Index Register X INX
Increment Index Register Y INY
Jump to Subroutine Long (Inter-Bank) JSL
Jump to Subroutine JSR
Load Accumulator from Memory LDA
Load Index Register X from Memory LDX
Load Index Register Y from Memory LDY
Logical Shift Memory or Accumulator Right LSR
Figure 18-6 LSR
Block Move Previous MVP
OR Accumulator with Memory ORA
Push Effective Absolute Address PEA
Push Effective Indirect Address PEI
Push Effective PC Relative Indirect Address PER
Push Data Bank Register PHB
Push Direct Page Register PHD
Push Program Bank Register PHK
Push Processor Status Register PHP
Push Index Register PHX
Push Index Register PHY
Pull Data Bank Register PLB
Pull Direct Page Register PLD
Pull Status Flags PLP
Pull Index Register X from Stack PLX
Pull Index Register Y from Stack PLY
Reset Status Bits REP
Rotate Memory or Accumulator Left ROL
Figure 18-8 ROL
Rotate Memory or Accumulator Right ROR
Figure 18-9 ROR
Return from Interrupt RTI
Return from Subroutine Long RTL
Figure 18-11 Stack before RTL
Return from Subroutine RTS
Figure 18-12 Stack before RTS
Subtract with Borrow from Accumulator SBC
Set Decimal Mode Flag SED
Set Interrupt Disable Flag SEI
Store Accumulator to Memory STA
Stop the Processor STP
Store Index Register X to Memory STX
Store Index Register Y to Memory STY
Store Zero to Memory STZ
Transfer Accumulator to Index Register X TAX
Transfer Accumulator to Index Register Y TAY
Transfer 16-Bit Accumulator to Direct Page Register TCD
Transfer Accumulator to Stack Pointer TCS
Transfer Direct Page Register to 16-Bit Accumulator TDC
Test and Reset Memory Bits Against Accumulator TRB
Test and Set Memory Bits Against Accumulator TSB
Transfer Stack Pointer to 16-Bit Accumulator TSC
Transfer Stack Pointer to Index Register X TSX
Transfer Index Register X to Accumulator TXA
Transfer Index Register X to Stack Pointer TXS
Transfer Index Register X to Y TXY
Transfer Index Register Y to Accumulator TYA
Transfer Index register Y to X TYX
Wait for Interrupt WAI
Reserved for Future Expansion WDM
Exchange the B and A Accumulators XBA
Exchange Carry and Emulation Bits XCE
19) Chapter Nineteen
Instruction Lists
Addressing mode box:
Operation column:
Op Code Matrix Legend
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