USB interface can be explained with electricaland mechanical interfaces. The signal and power aretransferred over a four wire cable consisting of: VDD,D+, D- and GND. Packets are transferred over D+ andD- wires whereas VDD and GND deliver power to thedevices. USB 2.0 supports three data rates: High speed(480 Mbps), Full speed (12 Mbps) and Low speed (1.5Mbps). USB physical topology consists of connectingthe downstream hub port to the upstream port of another hub or to a device. All devices have anupstream connection. Upstream and downstreamconnectors are not mechanically interchangeable.
USB is a polled bus and host controller initiates all transactions. Most bus transactions involvetransmission of three packets. They are token packet,data packet and handshake packet. Each transaction isinitiated by host controller. On scheduled basis, it sendsa packet describing the type and direction of transfer,device address and end point number. This packet isreferred as token packet. Device then selects itself bydecoding the appropriate address fields. Data istransferred either from host to device or from a deviceto host. The direction of data transfer is specified in thetoken packet. The source of the transaction then sendsthe data packet or indicates it has no data packets tosend. The destination responds with a handshake packet to indicate whether the transaction wassuccessful.
Data Flow Types
USB supports data and control exchange between host and the device as a set of either uni-directional or bi-directional pipes. USB data transfer takes place between the host software and a particular endpoint on a USB device. End points can be describedas sources or sinks of data. Endpoints occur at the endof the USB communication channel. USB 2.0 supports16 end points. All devices must support endpoint zero.This endpoint receives all of the device control andstatus requests during enumeration and throughout theduration when the device is operational on the bus.Endpoints 1-15 are used for data transfers.USB architecture supports four basic types of data transfers:
Control Transfers: These are used to configurea device at the time of attachment and for other device specific purposes.
Bulk Transfers: These are generated or consumed in relatively large and burstyquantities. Bulk data rate is sequential.Reliable data exchange is ensured by usingerror detection and invoking a limited number of retries.
Interrupt Transfers: These are used for timely but reliable delivery of data. These transfersinclude error detection and retransmission of data.
Isochronous Transfers: These occupy a pre-negotiated amount of USB bandwidth. Theseusually contain time sensitive information, butthey do not include error detection andretransmission.
This section describes the operation of USBfor normal data transfer between a host and a device.
Always a session is started by USB host. Itwaits for VBUS signals (avalid and vbusvalid)to rise and enters into full speed mode.
It then waits for device connection andgenerates connect interrupt when device getsconnected.
Device in the meantime waits to see itsconnection registered on linestate. Once itsconnection is registered, it enters into fullspeed mode.
Host then starts sending reset to the deviceand enters into high speed mode. Host startshigh speed mode handshake by sending chirpsJ (linestate – 01) and K (linestate -10).
After the handshake, device enters into highspeed mode and generates reset interrupt.
After the above configuration, endpoints areenabled and packets are transferred betweenthe enabled endpoints.III.
CHALLENGES IN USB VERIFICATIONVerification of USB can be done at IP level, IPsubsystem level and at SoC level.
IP level Verification
At IP level verification (usually at RTL level),USB IP will be provided by the IP vendors. It is theresponsibility of the verification engineer to build thetest-bench for the verification. The block diagram of atest-bench for verification of USB at IP level is givenin figure 1
.A processor is required to configure USB for data transfers and for USB to operate in various modes.To store data and instructions, data and instructionmemory associated with the processor are required.Interconnect such as OCP (Open Core Protocol) isrequired to connect the memories and processor withthe USB. Interconnects come as separate IPs. So theyhave to be integrated into the environment. A USB hostcan be verified only when there is a device from or to
Ms.Priyamvada Deshapande* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIESVol No. 8, Issue No. 1, 049 - 053ISSN: 2230-7818@ 2011 http://www.ijaest.iserp.org. All rights Reserved.Page 50