AN ABSTRACT OF THE DISSERTATION OF David Hong for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented

on November 5, 2008. Title: Fabrication and Characterization of Thin-lm Transistor Materials and Devices.

Abstract approved: John F. Wager

A class of inorganic thin-lm transistor (TFT) semiconductor materials has emerged involving oxides composed of post-transitional cations with (n-1)d10 ns0 (n4) electronic congurations. This thesis is devoted to the pursuit of topics involving the development of these materials for TFT applications: Deposition of zinc oxide and zinc tin oxide semiconductor layers via reactive sputtering from a metal target, and the characterization of indium gallium zinc oxide (IGZO)-based TFTs utilizing various insulator materials as the gate dielectric. The rst topic involves the deposition of oxide semiconductor layers via reactive sputtering from a metal target. Two oxide semiconductors are utilized for fabricating TFTs via reactive sputtering from a metal target: zinc oxide and zinc tin oxide. With optimized processing parameters, zinc oxide and zinc tin oxide via this deposition method exhibit similar characteristics to TFTs fabricated via sputtering from a ceramic target. Additionally the effects of gate capacitance density and gate dielectric material are explored utilizing TFTs with IGZO as the semiconductor layers. IGZO-based TFTs exhibit ideal behavior with improved TFT performance such as higher current drive at a given overvoltage, a decrease in the subthreshold swing, and a decrease in the magnitude of the turn-on voltage. Additionally it is shown that silicon dioxide is the preferred dielectric material, with silicon nitride a poor choice for oxide-based TFTs.

Finally a simple method to characterize the band tail state distribution near the conduction band minimum of a semiconductor by analyzing two-terminal current-voltage characteristics of a TFT with a oating gate is presented. The characteristics trap energy (ET ) as a function of post-deposition annealing temperature is shown to correlate very well with IGZO TFT performance, with a lower value of ET , corresponding to a more abrupt distribution of band tail states, correlating with improved TFT mobility. It is shown that as the post-deposition anneal temperature increases, the total number of band tail states does not change signicantly, however the energy distribution of these states approaches that of a crystalline material.

Copyright by David Hong November 5, 2008 All Rights Reserved

Fabrication and Characterization of Thin-lm Transistor Materials and Devices by David Hong

A DISSERTATION submitted to Oregon State University

in partial fulllment of the requirements for the degree of Doctor of Philosophy

Presented November 5, 2008 Commencement June 2009

Doctor of Philosophy dissertation of David Hong presented on November 5, 2008

APPROVED:

Major Professor, representing Electrical and Computer Engineering

Director of the School of Electrical Engineering and Computer Science

Dean of the Graduate School

I understand that my dissertation will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my dissertation to any reader upon request.

David Hong, Author

ACKNOWLEDGMENTS

I would like to thank my family for their support and encouragement throughout my education and life. They have instilled in me a work ethic and ambition that has led me this far. I would also like to thank all of my friends and coworkers who have contributed greatly during my graduate program. Several key people are Dr. Hai Chiang and Dr. Jeff Bender, who have been great resources for encouragement and cromulent insight into many topics as well as a great sounding board for my bizarre ideas. Professor John The Bossman Wager has provided great direction and discussion as well as an endless supply of enthusiasm and energy. Chris Tasker provided a work ethic to follow, as well as great direction and support in and outside of the cleanroom. Additionally, Manfred Dittrich has provided exceptional fabrication work and mechanical knowledge as well as great discussions ranging from politics and religion to football and the proper usage of threading taps. A number of industry people deserve acknowledgements. Two specic people I would like to mention are Randy Hoffman, inventor of the inorganic transparent thin-lm transistor, and Greg Herman, both of whom have been great resources. In addition to providing many of the substrates used for this dissertation, they have provided a high level of discussion and I am grateful for their time and energy. This work was supported by the Hewlett-Packard Company, the Defense Advanced Research Projects Agency (MEMS/NEMS: Science and Technology Fundamentals), the United States Display Consortium, and the NSF (IGERT grant no. 0549503).

To the optimist the glass is half full. To the pessimist the glass is half empty. To the engineer, the glass is twice as big as it needs to be. -unknown

TABLE OF CONTENTS Page 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. OXIDE SEMICONDUCTORS AND THIN-FILM TRANSISTORS . . . . . . . . . 2.1 Oxide semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2 1 4 4

Transparent conducting oxides overview . . . . . . . . . . . . . . . . . . . . . . . 4 Zinc oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Amorphous oxide semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zinc tin oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Indium gallium zinc oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Oxide semiconductor devices: Thin-lm transistors. . . . . . . . . . . . . . . . . . . 14 2.2.1 Thin-lm transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Oxide semiconductor-based thin-lm transistors . . . . . . . . . . . . . . . . 2.2.2.1 TFTs with simple oxide layers: ZnO . . . . . . . . . . . . . . . . . . . 2.2.2.2 TFTs with simple oxide layers: In2 O3 , SnO2 , Ga2 O3 . . . 2.2.2.3 TFTs with multicomponent oxide layers: ZTO . . . . . . . . . 2.2.2.4 TFTs with multicomponent oxide layers: ZIO . . . . . . . . . . 2.2.2.5 TFTs with multicomponent oxide layers: IGO . . . . . . . . . 2.2.2.6 TFTs with multicomponent oxide layers: IGZO . . . . . . . . 14 16 16 20 21 23 25 26

2.3

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3. TFT FABRICATION AND CHARACTERIZATION . . . . . . . . . . . . . . . . . . . . . . 30 3.1 Thin-lm deposition and processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.3 Evaporation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sputtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plasma-enhanced chemical vapor deposition (PECVD) . . . . . . . . . Atomic layer deposition (ALD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Post-deposition thermal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 31 34 35 36

Hall measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thin-lm transistor fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TABLE OF CONTENTS (Continued) Page 3.3.1 Fully-transparent TTFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 Non-transparent TFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 3.5 Transistor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thin-lm transistor device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.1 3.5.2 3.5.3 3.5.4 3.6 DC current-voltage measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Threshold voltage and turn-on voltage . . . . . . . . . . . . . . . . . . . . . . . . . Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drain current swing and drain current on-to-off ratio . . . . . . . . . . . . 46 48 50 57

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4. REACTIVE SPUTTERING OF OXIDE SEMICONDUCTORS . . . . . . . . . . . . 60 4.1 4.2 4.3 4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Reactive Zinc Oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reactive Zinc Tin Oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5. THIN-FILM TRANSISTOR DIELECTRIC PERFORMANCE . . . . . . . . . . . . . 76 5.1 5.2 5.3 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Experimental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chemical Vapor Deposited (CVD) Silicon Dioxide . . . . . . . . . . . . . . . . . . . 79 Silicon Dioxide, Aluminum Oxide, and Silicon Nitride . . . . . . . . . . . . . . . 88 Silane and Tetraethyl Orthosilicate (TEOS)-based CVD . . . . . . . . . . . . . . . 98

TABLE OF CONTENTS (Continued) Page 5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6. OXIDE SEMICONDUCTOR THIN-FILM TRANSISTOR TWO-TERMINAL ASSESSMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Experimental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Transistor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Metal-Semiconductor-Metal Current-Voltage Characteristics . . . . . . . . . . 104 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7. CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK . . . . 114 7.0.1 Recommendations for future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LIST OF FIGURES Figure 3.1 Page

TFT structures used for the research discussed in this thesis, including (a) fully-transparent thin-lm transistor and (b) non-transparent thinlm transistor.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (a)The basic structure of a TFT and corresponding energy band diagrams as viewed through the gate for several biasing conditions: (b) equilibrium, (c) VGS <0 V, and (d) VGS >0 V . . . . . . . . . . . . . . . . . . . . . . . . . 43 Four general thin-lm transistor congurations, including: (a) staggered bottom-gate, (b) coplanar bottom-gate, (c) staggered top-gate, and (d) coplanar top-gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Simplied timing diagram illustrating the applied voltage to the transistor as a function of time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output conductance-gate-to-source voltage (gD -VGS ) characteristic illustrating threshold voltage estimation via extrapolation of the linear portion of this curve to the VGS -axis intercept for an indium gallium zinc oxide semiconductor layer TFT with a width-to-length ratio of 10:1. gD is assessed at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Log(ID -VGS ) transfer characteristics showing the turn-on voltage, VON , and the threshold voltage, VT for the same device as shown in Fig. 3.5. The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Extracted average mobility (middle-black,) saturation mobility (topdark gray,) and saturation-average mobility (bottom-light gray) characteristics for a single IGZO-based thin-lm transistor. . . . . . . . . . . . . . . . . 56 Log(ID -VGS ) transfer characteristics showing the drain current swing, S, and the drain current on-to-off ratio, IONOFF for the same device D as shown in Fig. 3.5. The TFT is measured at VDS = 30 V. . . . . . . . . . . . . . 58 Cross sectional and plan view of a typical bottom-gate TFT. . . . . . . . . . . . . 62 Drain current-drain voltage (ID -VDS ) characteristics of a zinc oxide TFT which is fabricated near room temperature, i.e., without intentional substrate heating. VGS is decreased from 40 V (top curve, showing maximum current) to 0 V in 10 V steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Incremental mobility-gate voltage characteristics of a zinc oxide TFT which is fabricated near room temperature, i.e., without intentional substrate heating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.2

3.3

3.4 3.5

3.6

3.7

3.8

4.1 4.2

4.3

LIST OF FIGURES (Continued) Figure 4.4 Page

Log(ID )VGS characteristics obtained at VDS = 40 V for two zinc tin oxide TFTs fabricated via reactive rf sputtering which are subjected to a 300 C and 500 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Incremental mobility as a function of oxygen partial pressure for zinc tin oxide TFTs which are subjected to a 300 C and 500 C postdeposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Log(ID )VGS characteristics obtained at VDS = 40 V for two zinc tin oxide TFTs fabricated via reactive dc sputtering which are subjected to a 300 C and 500 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DC bias on the target as a function of oxygen partial pressure at a constant sputtering pressure of 30 mTorr and constant power of 50 W. A forward sweep (increasing oxygen partial pressure), backward sweep (decreasing oxygen partial pressure), and the region of optimal zinc tin oxide deposition are shown.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Simplied cross-sectional view of the device structure used for this chapter. SiO2 is deposited via PECVD from a silane source, the gate electrode stack and IGZO are deposited via magnetron sputtering, and aluminum pads are deposited via thermal evaporation. . . . . . . . . . . . . . . . . . 78 Log(ID )-VGS transfer characteristics for IGZO-based TFTs utilizing thermally grown silicon dioxide and CVD grown silicon dioxide as the gate insulator. The IGZO semiconductor layer is post-deposition annealed in air at 500 C. (inset) ID -VGS transfer characteristics for the same devices, plotted on a linear scale. The TFTs are measured at VDS = 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Extracted incremental mobility characteristics for IGZO-based TFTs utilizing thermally grown silicon dioxide and PECVD grown silicon dioxide as the gate insulator. The IGZO semiconductor layer is postdeposition annealed in air at 500 C. at 500 , as shown in Fig. 5.2. . . . . 81 Log(ID -VGS VON ) transfer characteristics for IGZO-based TFTs utilizing various thicknesses of silicon dioxide as the gate insulator. All TFTs are measured at VDS = 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Extracted incremental mobility INC as a function of gate-to-source voltage for IGZO-based TFTs utilizing various thicknesses of CVD silicon dioxide as the gate insulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.5

4.6

4.7

5.1

5.2

5.3

5.4

5.5

LIST OF FIGURES (Continued) Figure 5.6 5.7 Page

Extracted turn-on-voltage VON as a function of CVD silicon dioxide thickness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Subthreshold swing as a function of CVD silicon dioxide thicknesss for IGZO-based TFTs annealed at 300 C and 500 C The interface state density for each annealing temperature is also indicated.. . . . . . . . . . 87 Log(ID )-VGS transfer characteristics for IGZO-based TFTs utilizing thermally grown silicon dioxide as the gate insulator. The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Log(ID )-VGS transfer characteristics for IGZO-based TFTs utilizing CVD silicon dioxide as the gate insulator. The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.8

5.9

5.10 Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing ALD deposited aluminum oxide:titanium oxide as the gate insulator. The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.11 Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing ALD deposited aluminum oxide:titanium oxide as the gate insulator. For this TFT, the aluminum oxide:titanium oxide is annealed to 500 C prior to the semiconductor deposition, and the TFT stack is annealed at 300 C after the semiconductor deposition. The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.12 Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing CVD deposited silicon nitride as the gate insulator. The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.13 Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing thermal silicon dioxide, CVD deposited silicon dioxide from a silane (SiH4 ) precursor and CVD via a TEOS (SiC8 H20 O4 ) precursor. The TFTs are measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.1 Cross sectional view of the test structure used for this chapter. The silicon and silicon dioxide constitute the gate electrode and gate dielectric, respectively. The aluminum pads are the source/drain contacts and indium gallium zinc oxide (IGZO) constitutes the semiconductor layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

LIST OF FIGURES (Continued) Figure 6.2 Page

Log(ID )-VGS transfer characteristics obtained at VDS = 30 V for an IGZO TFT post-deposition annealed at 300 C. (inset) Drain currentdrain voltage (ID -VDS ) output characteristics for the same device. VGS is decreased from 30 V (top curve, showing maximum current) to 0 V in 10 V steps. Note that the VGS = 10 V and 0 V curves overlap with the x-axis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Current-voltage characteristics for an IGZO TFT operated as a twoterminal M-S-M (Al-IGZO-Al) device. Voltage is applied to the drain with the source grounded for two situations: with the gate electrode oating and with VGS = 0 V. The IGZO TFT employed is subjected to a 300 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Current-voltage characteristics of four IGZO TFTs operated as twoterminal M-S-M (Al-IGZO-Al). Voltage is applied to the drain with the source grounded and the gate electrode oating. Four different postdeposition anneal temperatures (300(diamond), 400(square), 500(triangle), 600(X) C) are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Estimated band tail state density distribution (Nt (E)) near the conduction band minimum for IGZO annealed at 300, 400, 500, 600 C. . . . . . . . 110 Estimated band tail state density distribution (Nt (E)) near the conduction band minimum for IGZO annealed at 300, 400, 500, 600 C assuming a constant value of N0 for all annealing temperatures. . . . . . . . . . . 112

6.3

6.4

6.5 6.6

LIST OF TABLES Table 2.1 Typical properties of various n-type transparent conducting oxide semiopt conductors. Eg represents the optical band gap, represents the electron afnity, T represents the percentage transmitted in the visible portion of the electromagnetic spectrum, m /me represents the density of states effective mass, H represents the Hall mobility, n represents the carrier concentration, and represents the resistivity. . . . . . . . . . . . . . . . . . . . Page

6.1

A summary of IGZO TFT properties for various post-deposition anneal temperatures. Incremental mobility INC and turn-on voltage (VON ) are obtained from three-terminal TFT assessment while space-chargelimited parameters, i.e., characteristic trap energy and temperature, ET and Tt , total trap density, Nt , trap concentration per unit energy evaluated at the conduction band minimum, N0 , are obtained from twoterminal measurements between the source and drain with the gate oating. The following values are used in the estimation of Nt and N0 : NC = 5.0 1018 cm3 , = 20 cm2 V1 s1 , and S = 1.0 1010 Fcm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

FABRICATION AND CHARACTERIZATION OF THIN-FILM TRANSISTOR MATERIALS AND DEVICES

1. INTRODUCTION

Oxide semiconductors composed of post-transition cations with (n-1)d10 ns0 (n4) electronic congurations, such as zinc tin oxide, constitute an interesting class of materials since they are often transparent in the visible portion of the electromagnetic spectrum as a result of their large band gaps (> 3.0 eV), yet also possess relatively high electron mobilities in spite of their amorphous character. [1, 2, 3] When employed as a semiconductor layer in TFT applications, such materials, namely zinc oxide, zinc tin oxide, zinc indium oxide, and indium gallium zinc oxide, have yielded high-performance thin-lm transistors (TFTs). [4, 5, 6, 7, 8] Research within this area of oxide electronics has ballooned in recent years, specifically with regard towards the commercialization of oxide-based electronics for use in display technology. [9, 10, 11, 12] These reports primarily focus on the process optimization of the oxide semiconductor for use in TFTs, showing that oxygen content in the ambient during deposition and processing temperature are the key factors affecting TFT performance. [9, 13, 14, 15] Additionally several reports have included demonstration vehicles utilizing oxide-based electronics for use in OLED and E-ink displays. Recently at the 2008 Society of Information Display conference, a 12.1 inch OLED display was demonstrated by Samsung SDI that used IGZO-based TFTs as the active matrix

2 backplane. Functional devices have also been fabricated on plastic substrates for exible electronic applications. [16, 12] Furthermore, issues such as TFT bias stress stability [17, 18, 19, 20] short channel effects [21], light sensitivity [22] and contact resistance [12, 18] have been explored. In addition to display control elements, several other applications have been hypothesized. Depending on deposition conditions, these oxide semiconductors can show sensitivity to humidity or specic gases which make them applicable as sensors. [23, 24, 25, 26] Additionally due to their high performance and ability to be built upon each other in a vertical arrangement, oxide-based TFTs are possible sense and control elements for high density memory applications. [21] Three primary goals are pursued in this thesis, all related to the development of oxide based TFTs or TTFTs: processing parameter effects on reactive sputtering of zinc oxide and zinc tin oxide are explored, TFT characteristics as a function of gate capacitance density are evaluated, and the material choice for use as the gate dielectric are explored. The structure of this thesis is as follows. Chapter 2 contains a review of the pertinent literature and provides the technical background necessary to establish a context within which experimental results can be discussed. Chapter 3 provides a description of important fabrication tools and techniques employed, followed by a discussion of TFT operation and relevant electrical TFT characterization methodology and gure-of-merits. Chapter 4 is devoted to evaluation of processing parameter effects on reactively sputtered zinc oxide and zinc tin oxide. Chapter 5 presents a study evaluating TFT performance

3 utilizing indium gallium zinc oxide as the semiconductor layer with varying thicknesses of silicon dioxide and various materials as the gate dielectric. Chapter 6 presents an analysis of band tail state distribution in IGZO semiconductor after post-deposition anneals at various temperatures. Finally, Chapter 7 contains conclusions and recommendations for future work.

2. OXIDE SEMICONDUCTORS AND THIN-FILM TRANSISTORS

This chapter rst provides an overview of oxide semiconductors. Then, the morphology and properties of several oxide semiconductors (zinc oxide, zinc tin oxide (ZTO) and indium gallium zinc oxide (IGZO) are discussed in more detail, as they are used extensively in this work. Finally, the electrical properties of several oxide semiconductorbased TFTs are reviewed.

2.1

Oxide semiconductors
This section rst summarizes the properties of well-known degenerate oxide semi-

conductors or transparent conducting oxides (TCOs). Then, several oxide semiconductors (zinc oxide, ZTO, and IGZO) are discussed in more detail, as they are used extensively in this work.

2.1.1 Transparent conducting oxides overview

Transparent conducting oxides (TCOs) constitutes a class of materials which exhibit a large band gap (typically Eg 3.1 eV, due to the large electronegativity of oxygen in n-TCOs [27]), rendering them highly transparent (80-90%) in the optical portion of the electromagnetic spectrum, as well as high conductivity. In these materials, n-type conduction is derived from two sources: the creation of point defects (such as oxygen vacancies and/or metal interstitials) or extrinsic substitutional doping (typically on the cation site). The prototypical TCO is zinc oxide, in which

5 case the point defect is due to either oxygen vacancies or zinc interstitials. In the case of an oxygen vacancy, two valence band sites are not present, therefore the two electrons that would have occupied those sites now occupy conduction band sites and the lattice point corresponding to the oxygen vacancy is left with a localized 2+ charge. In the alternative case of a zinc interstitial, a zinc neutral residing on an interstitial site is reduced to a more thermodynamically stable 2+ state in the process donating two electrons to the conduction band. Zinc oxide can also be extrinsically doped, typically with an aluminum ion on a zinc site. In this case, a 3+ aluminum sits on a 2+ site, resulting in one additional electron in the conduction band and a localized 1+ site. Typically point defect concentrations can be modied during the deposition process by appropriate selection of processing parameters or by subjecting the sample to an oxidizing or reducing post-deposition anneal. The drawbacks of using intrinsic defects as the primary source of conduction are the possibility of lm re-oxidation and (typically) lower conductivity compared to extrinsically doped lms. The minimum theoretical resistivity limit for n-type TCOs has been predicted by Bellingham et al. as 4 105 cm. [28] This limit is a consequence of transport that is constrained by ionized impurity scattering ( < 90 cm2 V1 s1 ) and carrier concentration limitations due to increasing optical reection with increasing carrier concentration (n < 2 1021 cm3 for >90% optical transmission). Experimental results for single crystal In2 O3 :Sn have approached this theoretical resistivity limit, yielding a minimum resistivity of 7.7105 cm ( = 42 cm2 V1 s1 , n = 1.9 1021 cm3 ). [29]

6 TCOs are currently utilized in a number of passive applications, including thin-lm solar cells and at-panel displays. SnO2 is commonly employed in applications where patterning is not required (as SnO2 is difcult to chemically wet etch) and when high levels of conductivity are not required. Of the commercially available TCOs, In2 O3 :Sn is the most conductive. In2 O3 :Sn is also easier to etch than SnO2 and can be deposited at lower temperatures. Unfortunately, the availability of indium is limited, as it is a byproduct of mining ores for other metals (such as zinc and lead). [30] Moreover, indium is not as abundant as other metals; there is 1000 times more zinc (132 ppm) than indium (0.1 ppm) in the earths crust. [31, 32] Thus, efforts are being made to nd a suitable replacement for In2 O3 :Sn. Among the materials being explored is ZnO:Al, which is attractive for its ease of etchability, stability in a hydrogen plasma, and low process temperature requirement. [33, 34] Table 2.1 summarizes optical and physical properties of various n-type TCOs. The tabulated electron afnity, , is the difference between the vacuum level and conduction band minimum and is assumed to be approximately equal to the work function (the difference between the vacuum level and the Fermi level) for these degenerate semiconductors. Also note that two TCOs, CuInO2 and ZnO, exhibit bipolar conductivity. A summary of p-type TCOs can be found elsewhere. [35]

Table 2.1: Typical properties of various n-type transparent conducting oxide semiconductors. Eg represents the optical band gap, represents the electron afnity, T represents the percentage transmitted in the visible portion of the electromagnetic spectrum, m /me represents the density of states effective mass, H represents the Hall mobility, n represents the carrier concentration, and represents the resistivity.
opt

opt

Material 0.18-0.25 0.29-0.42 0.35

(eV) 4.26 3.7 5.4 4.5 4.5-5 4.9 5.3 0.16-0.26 0.2 0.23l , 0.30t 0.27 0.4

CdO CuAlO Cd2 SnO4 In2 O3 InGaO3 InGaZnO4 SnO2 ZnO Ti1X NbX O2 Zn2 In2 O5 ZnSnO3 Zn2 SnO4

Eg (eV) 2.2-2.6 3.49 2.9-3.1 3.7 3.3 3.5 3.6 3.2-3.3 3.2 2.9 3.5 3.3-3.9

T (%) 75 60-70 90 80-90 90 80-90 80-90 80-90 95 80 80 90

m /me H (cm2 V1 sec1 ) 220 10 35-60 10-40 10 24 5-30 5-50 10 12-20 7-12 12-26 n (cm3 ) 1019 -1021 1x1018 1-7x1020 1021 1020 1020 1020 1021 2-40x1020 2.4-5x1020 1020 6-30x1018

( cm) 2x103 1 1.4-12x104 104 2.5x103 2x103 103 104 2x104 1-4x103 4-5x103 1-5x102

References [31, 36] [37] [31, 38, 39, 40] [32, 40, 41] [42, 43] [44, 45, 46] [32, 40, 47] [32, 40, 43] [48] [39, 43, 49] [43, 50, 51] [39, 52, 53]

Bipolar conductive material [54, 55, 56] l Longitudinal effective mass t Transverse effective mass

2.1.2 Zinc oxide

Zinc oxide is one of the most widely used oxide semiconductors. In addition to its utilization as a TCO material, zinc oxide is used in many health care products due to its absorption of the UV portion of the electromagnetic spectrum, light-emitting devices, as well as ceramic-based varistors. The optical band gap for zinc oxide is reported to be between 3.1 and 3.3 eV. Zinc oxide is typically polycrystalline, with a wurtzite structure and preferential grain growth in the c-axis direction (normal to the substrate), even on amorphous substrates. ZnO thin lms have been deposited using a number of methods, including reactive sputtering (DC [57], RF [58], ion beam [19]), activated reactive evaporation (ARE) [59], spray pyrolysis [60], metalorganic chemical vapor deposition (MOCVD) [61], and electrochemical reaction [62]. More recently zinc oxide thin lms have been fabricated from solution-based precursors. [63, 64, 65] In these lms a solution is spin-coated onto the substrate and annealed to drive off the solvent. Zinc oxide is typically an n-type semiconductor, due to an inherent nature of forming an oxygen decient lm. However, recent reports have claimed that p-type doping of the material can be achieved. A high degree of n-type conductivity (> 5000 1 cm1 ) is attainable in zinc oxide, due to intrinsic defects, intentional donor doping (Al, In, Ga, B, F) or a combination thereof. Reported thin-lm Hall electron mobilities are typically >20 to 30 cm2 V1 s1 ; the maximum mobility obtainable in ZnO single crystals is >200 cm2 V1 s1 . There is not a consensus in the literature as to which intrinsic defect (O vacancy or Zn interstitial) is responsible for intrinsic n-type conductivity. P-type conduc-

9 tivity has not been convincingly or reproducibly demonstrated, although compensation of n-type doping through the introduction of acceptor impurities is possible. This difculty in obtaining p-type ZnO is attributed to the phenomenon of self-compensation. [35]

2.1.3 Amorphous oxide semiconductors

Amorphous oxides composed of post-transition metal cations with (n-1)d10 ns0 , where n4, electronic congurations constitute an interesting subcategory of transparent conductors, since they possess relatively high electron mobilities despite their amorphous character. [66, 67, 68] Examples of such materials include indium oxide doped with tin (ITO) [69] and zinc tin oxide [70] for which amorphous-state mobilities as large as 40 and 30 cm2 V1 s1 , respectively, have been reported. Such high mobilities in an amorphous material are likely a consequence of a conduction band primarily derived from spherically symmetric, post-transition metal cation ns orbitals. Such orbitals have large radii, leading to a high degree of overlap between adjacent orbitals and considerable band dispersion. Moreover, the spherical symmetry of an s orbital makes delocalized electronic transport less sensitive to local and extended structural order as compared with band formation from anisotropic p or d orbitals. Furthermore, compared to binary oxide semiconductors, multicomponent oxide semiconductors increase the likelihood that the structure will remain amorphous over a wide range of processing conditions. Zinc tin oxide and indium gallium zinc oxide are discussed below, as these materials are used extensively in this work.

10

2.1.4 Zinc tin oxide

Zinc tin oxide (ZTO), which is sometimes referred to as zinc stannate, has recently received attention as an alternative TCO. Zinc tin oxide is most generally described as, (ZnO)x (SnO2 )1x , where 0 < x < 1. There are two crystalline forms of ZTO, trigonal ilmenite (ZnSnO3 , x = 0.5) [71] and spinel (Zn2 SnO4 , x = 0.66) [52]. As shown by Shen et al., powder mixtures with stoichiometry close to trigonal ilmenite ZTO (ZnSnO3 ) decompose to spinel ZTO (dizinc tin oxide, i.e. Zn2 SnO4 ) and SnO2 at calcination temperatures above 700 C. [72] Several aspects that make ZTO attractive are its low-cost nature (as zinc and tin are readily available materials), its chemical and electrical stability in highly concentrated (> 35%) HCl solutions and its physical robustness, [50, 53] i.e., no damage to the thin lm is visually apparent after scratching with the corner of a razor blade. The zinc tin oxide phase space has been examined by Moriga et al. using dc cosputtering from a ZnO and SnO2 :Sb (Sb2 O5 ) target. [73] For temperatures up to 350 C, lms with 0.33 x 0.66 were found to be amorphous. These amorphous lms exhibit a constant Hall mobility of 10 cm2 V1 s1 . The carrier concentration decreases linearly as the Zn concentration is increased from x = 0.33 (ZnSn2 O5 ) to 0.66 (Zn2 SnO4 ). The minimum resistivity is 4 102 cm and occurs at x = 0.33. Other authors have shown that crystalline spinel ZTO (Zn2 SnO4 ) thin lms are attainable through the use of a variety of deposition techniques, including electron beam evaporation, [74] rf magnetron sputtering, [39, 52, 53, 75, 76] chemical vapor deposition, [53, 77] and spray pyrolysis [23]. In actuality, rf magnetron sputtered Zn2 SnO4 has been

11 found to have an inverse spinel structure, in which half of the Zn cations exchange sites with Sn cations. [53, 75] Optical and electrical properties of crystalline ZTO are tabulated in Table 2.1. Spinel ZTO is a direct band gap material with a fundamental band gap of 3.35 eV. Spinel ZTO exhibits a pronounced Burstein-Moss shift. Concomitant with the Burstein-Moss shift is a small relative electron effective mass (0.16me ). Thus, one would expect the mobility to be quite large since mobility is inversely proportional to the effective mass, i.e., = q , m (2.1)

where is the relaxation time and m the effective mass. However, the maximum measured Hall mobility for a rf magnetron sputtered thin-lm is only 26 cm2 V1 sec1 . Thin lms fabricated to date have been limited by intra-grain defects due to atomic disorder, which may not be alleviated even in single crystal growth. [52, 53, 75] Applications of ZTO have been somewhat limited due to its low conductivity, but ZTO has been employed in thin-lm solar cell applications [78] and humidity and gas sensors [23, 24, 25, 26].

2.1.5 Indium gallium zinc oxide

Indium gallium zinc oxide (IGZO) is a wide band gap (3.5 eV), n-type semiconductors; its stoichiometry can be generally described as In2x Ga22x (ZnO)k , where 0 < x < 1 and k is an integer that is greater than 0. [46, 44, 45, 79, 80, 81, 82, 83] Single crystal indium gallium zinc oxide is composed of alternating layers of InO and GaZnO+ ; 2 4

12 the In3+ ion has octahedral coordination, the Ga3+ ion has pentagonal coordination, and the Zn2+ has tetragonal coordination. [45, 79, 80] Several groups have synthesized bulk samples with varying stoichiometry (both x and k) to appraise the solubility limits of the structure. [79, 80] The intriguing result is that, regardless of k, when x = 0.5 (equal proportions of In and Ga) the structure is preserved. In other words, x = 0.5 constitutes the base compound where all the In3+ ions are in the InO and all the Ga3+ ions are in the 2 GaZnO+ layer. 4 For k 3, the conductivity decreases as k is increased. This trend is observed in both bulk samples [80] and thin lms [81], indicating that the conductivity of indium gallium zinc oxide is primarily associated with the In 5s states. However, for k 4, the fraction of Zn becomes increasingly large and Zn begins to contribute to conduction. [81] Considering orbital overlap interaction and comparing the ionic radii of cations in the IGZO system is useful for understanding the shift in the conduction path. The ionic radii of Ga, In, and Zn are 1.27, 1.49, and 1.54 A, respectively. As the ionic radii of In and Zn are quite similar, it is not surprising that Zn contributes to conduction as the fraction of Zn becomes increasingly large. [81] The structure of single crystal and amorphous InGaZnO4 thin lms (250 nm) are examined using extended x-ray absorption ne structure (EXAFS), which is commonly employed to appraise short range order. [46, 84, 85] The nearest-neighbor distances for In-O, Ga-O, and Zn-O in the amorphous lm are 0.211, 0.200, and 0.195 nm, respectively. This short range ordering is similar to that of the single crystal structure (0.218, 0.193, and 0.193, respectively). However, it appears that medium range ordering (second

13 nearest-neighbor distances) near the Ga and Zn ions is lost in the amorphous lms. Ab initio calculations were performed and are in good agreement with the EXAFS results. Additional calculations show that the In-In second nearest-neighbor coordination number in the amorphous state varies with distance (i.e., 1 to 4 for distances of 0.32 to 0.4 nm) and is signicantly lower than in the crystalline structure, which has a coordination number of 6. This indicates that the selective (medium range) coordination of In-In is lost in the amorphous structure. From the experimental and calculated results, the coordination numbers of In-O, Ga-O, and Zn-O are deduced to be 5, 5, and 4, respectively. Finally, pseudoband calculations show that the conduction band minimum is composed of In 5s (consistent with the experimental results discussed in the previous paragraph) and that that amorphous IGZO has an isotropic effective mass of 0.2me . Amorphous IGZO has been employed in a light-emitting pn heterojunction. [86] The IGZO layer is deposited by pulsed laser deposition (PLD) at room temperature. The carrier concentration and mobility of this layer is 1 1019 cm3 and 5 cm2 V1 s1 . Indium gallium zinc oxide is chosen here for its reasonable conductivity at low processing temperatures and its large band gap (3.5 eV). Blue emission ( 430 nm peak) is observed from this pn heterojunction and is due to intrinsic exciton recombination in the single crystal p-LaCuOSe layer (which has a band gap, carrier concentration, and mobility of 2.8 eV, 1 1019 cm3 , and 8 cm2 V1 s1 , respectively).

14

2.2

Oxide semiconductor devices: Thin-lm transistors

As the primary goal of this work is to explore oxide semiconductor-based TFTs

a summary of oxide semiconductor-based TFTs is given. A discussion of TFT operation and gure-of-merits is included in Chapter 3. As the work in this eld is rapidly increasing, only the most noteworthy works are reviewed here.

2.2.1 Thin-lm transistors

Invention of the rst eld-effect device is often credited to J. E. Lilienfeld, who patented the concept in 1934. [87] However, development of the rst thin-lm transistor (TFT), as it is known today, is credited to P. K. Weimer (1962). [88] These initial ntype TFTs fabricated by Weimer used a top-gate staggered structure with microcrystalline CdS deposited via evaporation as the channel layer. Thermally evaporated SiO (silicon monoxide) was used as the gate dielectric and gold for the gate electrode and source and drain contacts. All patterning was done via shadow masks, channel lengths of 5 to 50 microns were achieved. These early devices exhibited eld-effect mobilities on the order of 1.1 cm2 V1 s1 and drain current on-to-off ratios of 101 . Since Weimers initial work, TFTs based on a wide variety of channel materials, including CdS, CdSe, amorphous and polycrystalline silicon, have been developed. Currently, the most dominant TFT technology is based on hydrogenated amorphous silicon (a-Si:H), which are commonly employed as control circuitry in active-matrix liquid crystal displays (AMLCDs). High performance a-Si:H TFTs typically have eld-effect mobil-

15 ities of approximately 1.5 to 2.0 cm2 V1 sec1 with a maximum processing temperature of 300 C. [89] A route towards silicon-based TFTs utilizing single crystal silicon has been demonstrated by Menard et al. [90] Beginning with a silicon-on-insulator wafer, micro and nano-scale patterns are etched within the silicon and released from the insulator layer. These micro and nano-sized silicon particles are suspended in an organic solution and subsequently transferred and cured onto a plastic substrate. TFTs fabricated utilizing this process are n-channel and exhibit mobilities as large as 120 cm2 V1 s1 and VON of -5 V. Multiple circuits have been implemented utilizing this technology: inverters exhibit a gain of 2.6 at a supply voltage of 3 V, 5 stage ring oscillator exhibit a frequency of 8 MHz at a supply voltage of 4 V, and a differential amplier consisting of a differential pair, current source and current mirror. [91] In addition to silicon TFTs, another class of TFTs consists of those which employ organic materials as the channel layer. [92] These materials exhibit mobilities of 103 -1 cm2 V1 s1 . However, the low mobility of these organic TFTs is offset by the low cost of deposition, such as spin coating or printing. In addition, the processing temperature of these devices is below 300 C, allowing for deposition onto plastic substrates. Most of these organic channel materials are p-type. However, an n-type organic TFT has been demonstrated using an organic channel layer. [93] This n-type organic TFT demonstrated mobilities of up to 0.1 cm2 V1 s1 . Augmenting organic TFTs, combinations of organics and inorganics, referred to as hybrid materials, have also been explored for TFT applications. [94] Hybrid materials

16 use a mixture of organic and inorganic chemicals to attain desired physical and chemical properties. TFTs made from a tin(II) iodide perovskite, (C6 H5 C2 H4 NH3 )2 SnI4 , have been fabricated with incremental mobilities of 0.61 cm2 V1 s1 .

2.2.2 Oxide semiconductor-based thin-lm transistors

Since the introduction of oxide semiconductor-based thin-lm transistors in 2003, a wide variety of n-type oxide materials have been employed for the semiconductor layer. These materials include several simple oxides (ZnO, SnO2 , and In2 O3 ) and several amorphous multicomponent oxides (ZTO, zinc indium oxide(ZIO), indium gallium oxide (IGO), and IGZO). The scope of this research includes discrete TFT performance, circuit integration (ring oscillators), and integration with other technologies (e-ink, liquid crystals, and organic light-emitting diodes). The following subsection does not detail each work. Instead, the general properties associated with each oxide semiconductor and the most noteworthy work is highlighted. References are provided for those interested in obtaining additional information.

2.2.2.1 TFTs with simple oxide layers: ZnO

ZnO was the rst and most widely employed oxide semiconductor for TFTs, with over 10 institutions publishing reports on its use. [95, 15, 96, 97, 4, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 63] These reports employ a variety of deposition techniques for fabrication, including rf sputtering, ion beam sputtering, solution-based deposition, and pulsed laser deposition (PLD).

17 The initial reports of ZnO-based TFTs by Masuda et al. and Hoffman et al. in 2003 ignited the research of transparent TFTs. These devices were fabricated with different deposition methods (PLD and ion beam sputtering) and utilized fairly high temperature processing (450 - 700 C). These devices utilized either atomic layer deposited aluminum oxide:titanium oxide or plasma enhanced chemical vapor deposited silicon nitride. The resultant devices exhibited drain current on-to-off ratios (ID
ono f f

) up to 107 and channel

mobilities in the range of 0.01 to 2.5 cm2 V1 s1 . Additionally, ambient light had little effect on device performance. More recently, several authors have explored ZnO-based TFTs with rf sputtering that do not require intentional post-deposition annealing treatments. [98, 102] It is interesting to note that these authors successfully implement drastically different deposition parameters for forming their ZnO layers (high pressure/low power and low pressure/high power for Carcia et al. and Fortunato et al., respectively). In these cases, e-beam evaporated aluminum oxide and atomic layer deposited aluminum oxide:titanium oxide are used as the gate dielectrics. The electrical properties of ZnO-based TFTs are shown to be strongly inuenced by the O2 partial pressure in the deposition ambient; TFTs with mobilities approaching 25 cm2 V1 s1 were demonstrated. Additionally, ZnO-based TFTs on exible polyimide substrates were also demonstrated. [98] Solution-based deposition techniques, including spin coating and chemical bath deposition have been employed to fabricate ZnO-based TFTs. [63, 64, 65] The reports using spin-coating employ a high temperature post-deposition anneal to attain adequate crystallization and device performance. Norris et al. spin a zinc nitrate precursor solution (zinc

18 nitrate hexahydrate and glycine) and anneal at 700 C. The channel mobility and ID
ono f f

of these devices is 0.2 cm2 V1 s1 and 107 , respectively. [63] Lee et al. incorporate zirconium isopropoxide in their sol-gel precursor to suppress the free carrier density of their lms. Spin-coated Zn0.97 Zr0.03 O TFTs annealed at 500 C exhibited channel mobilities, VT , and ID
ono f f

of 0.3 cm2 V1 s1 , 4.7 V, and 106 , respectively. [64] Cheng et al.

utilize a chemical bath containing zinc nitrate and dimethylamineborane at 60 C to grow ZnO lms. TFTs fabricated with these lms exhibited channel mobilities and ID 0.25 cm2 V1 s1 and 105 , respectively. [65] Contributions enhancing the understanding of oxide-based TFT operation have been made by Hossain et al. and Hoffman. [97, 4] Hossain et al. analyze grain boundary effects (modeled as a two-sided Schottky barrier) for polycrystalline ZnO TFTs. These simulations show a decrease in grain boundary barrier height with increasing free carrier concentration and a decrease in channel mobility as the number of grain boundaries in the channel increases. Hoffman explains the intricacies of mobility extraction and discusses mobility characteristics of ZnO-based TFTs. Understanding mobility extraction is essential to this work and is discussed in detail in Sec.3.4.3. Cross et al. report the bias-stress stability of zinc oxide based TFTs. [20] Biasstress instabilities are caused by two different mechanisms. Low eld instabilities are a result of charge trapping at or near the dielectric-semiconductor interface concurrent with negligible change in subthreshold swing characteristics. At higher elds, instabilities are the result of trap-state creation concurrent with degraded subthreshold swing characteristics. The demarkation between low-eld stress and high-eld stress is found to be 30
ono f f

of

19 V for devices with 150 nm thick silicon dioxide as the gate dielectric, corresponding to an applied electric eld of 2 MVcm1 . The threshold voltage shifted in the direction of the applied voltage, with a positive bias-stress inducing a positive shift and a negative bias-stress inducing a negative shift. Cross et al. report also on the bias-stress stability of zinc oxide based TFTs utilizing either a silicon dioxide or a silicon nitride gate dielectric. In these cases the gate dielectric is deposited via a high temperature process (>1000 C), with the semiconductor and source and drain deposited at room temperature. In these devices, the bias stability exhibited different characteristics, however silicon nitride appeared to exhibit better bias-stress stability. Levy et al. report on the fabrication of the gate dielectric and semiconductor layer via atomic layer deposition. [113] Zinc oxide TFTs are fabricated with temperatures below 200 C, exhibiting mobilities as high as 20 cm2 V1 s1 and no visible hysteresis. Additionally ring oscillators are demonstrated exhibiting 31 nS propagation delays through each stage. Hirao et al. and Park et al. have utilized ZnO-based TFTs in active-matrix displays. [103, 104] Hirao et al. have fabricated AMLCDs with staggered top-gate ZnO TFTs which utilize a SiNx gate insulator. These TFTs exhibit a channel mobility of 50 cm2 V1 s1 . Park et al. have fabricated a transparent AMOLED display with coplanar bottom-gate ZnO TFTs which utilize an Al2 O3 gate insulator. Additionally, the ZnO deposition process utilized by Park et al. is compatible with plastic substrates. These dis-

20 play prototypes show that ZnO TFTs can be integrated into useful applications and that multiple ZnO TFTs can operate simultaneously. Yamauchi et al. report on fabrication of an integrated zinc oxide TFT-OLED device. [114] Zinc oxide is deposited via sputtering. The OLED is deposited directly on the TFT drain material (aluminum doped zinc oxide), such that the aluminum doped zinc oxide constitutes both the drain for the TFT and electron injection material. When ITO is used as the drain material/OLED contact, no luminance is detected indicating that zinc oxide is necessary for electron injection.

2.2.2.2 TFTs with simple oxide layers: In2 O3 , SnO2 , Ga2 O3

SnO2 and In2 O3 are not commonly employed as the TFT semiconductor layer due to difculty in suppressing/controlling the carrier concentration, which leads to highly negative threshold voltages. To compensate for this, Presley et al. utilize extremely thin semiconductor layers (10-20 nm) to control VT of SnO2 -based TFTs. [115] Wang et al. address this issue through the use of ion-assisted deposition, in which the carrier concentration of the layer is controlled (1017 to 1020 cm3 in In2 O3 lms) by adjusting the O2 partial pressure and ion beam power. Using this technique, In2 O3 -based TFTs with organic self-assembled dielectrics were fabricated. [116] Additionally, Ga2 O3 is not commonly employed as a TFT semiconductor layer due to low mobility values. Matsuzaki et al. report on polycrystalline Ga2 O3 -based TFTs with eld-effect mobilities of 0.05 cm2 V1 s1 at a processing temperature of 550 C.

21 [117, 118] At higher processing temperatures, the Ga2 O3 -based TFTs exhibited no eldeffect induced conduction, indicative of a high trap concentration.

2.2.2.3 TFTs with multicomponent oxide layers: ZTO

Zinc tin oxide (ZTO)-based TFTs have been fabricated using a wide variety of methods, including rf sputtering, reactive dc sputtering, and plasma-assisted PLD. [13, 119, 17, 120, 12, 121] The initial ZTO-based TFTs (ZnSnO3 ) exhibited a channel mobility which approached 30 cm2 V1 s1 when subjected to a 600 C post-deposition anneal. [13] Since this initial report, researchers have explored the effects of varying ZTO stoichiometry [17, 120], integrated ZTO-based TFTs with transparent OLEDs, and demonstrated exible TFTs using ZTO. The effects of stoichiometry and annealing on electrical characteristics of ZTObased TFTs were explored by Hoffman. [120] Sputter targets of varying stoichiometry (Zn/(Zn + Sn) = 0.0, 0.33, 0.5, 0.67, and 1.0) were used for fabrication. The intermediate stoichiometries (Zn/(Zn + Sn) = 0.33, 0.5, and 0.67) and post-deposition anneal temperatures (400-600 C) produced devices with broad peak mobilities (approaching 30 cm2 V1 s1 ). The turn-on voltage decreases with increasing anneal temperature and decreasing ratios of Zn:Sn (with the inability to deplete any of the SnO2 devices). G rrn et al. explore the effect of stoichiometry (0.33 Zn/(Zn + Sn) 0.65) on o bias stress stability of ZTO-based TFTs. These devices were fabricated at 250400 C with plasma-assisted PLD. All transistors fabricated in this study exhibited minimal hysteresis and channel mobilities in the range of 514 cm2 V1 s1 . A constant voltage bias

22 stress of 10 V is applied for 60 ks; the test is interrupted every 100 s to measure transfer (ID VGS ) characteristics for threshold voltage and mobility extraction. Positive and negative VT shifts with respect to bias stress time were observed. Positive shifts in VT were accompanied by rigid shifts in the transfer characteristic, while negative shifts were accompanied by non-rigid shifts in the transfer characteristic and degradation in the subthreshold slope. The relative change in channel mobility during testing for all devices is less than 10% and does not correlate to the behavior of VT shifts. Zn/(Zn + Sn) = 0.36 resulted in optimal performance; a threshold voltage shift of 30 mV and minimal change in channel mobility is observed for this stoichiometry. G rrn et al. have studied the effects of illumination on the TFT performance of o ZTO-based TFTs. [22] Zinc tin oxide TFTs exhibit persistent photoconductivity in the form of a negative threshold voltage shift, increased off current, and decreased mobility when under illumination of 425 nm light at an intensity of 250 Wcm2 which mimics the effect of a blue LED. The effect of the illumination reached a steady state at 10 hours, while recovery back to initial device characteristics required 20 hours. G rrn et al. have integrated transparent ZTO-based TFTs with transparent OLEDs o as a rst step towards a transparent display. [119] For this demonstration, the OLED is fabricated atop the drain (which also serves as the cathode for the OLED) of the staggered bottom-gate ZTO and SU-8 photoresist is used for pixel denition. The ZTO semiconductor layer is deposited by plasma-assisted PLD, with a maximum processing temperature of 150 C. The channel mobility and threshold voltage range of these TFTs is 11 cm2 V1 s1 and -1 to 1 V, respectively.

23 Jackson et al. fabricated staggered bottom-gate ZTO-based TFTs on exible polyimide substrates. [12] These TFTs utilize a 375 nm thick SiON gate insulator. The ZTO semiconductor is subjected to a 250 C post-deposition anneal for 10 minutes. The channel mobility and threshold voltage are 14 cm2 V1 s1 and -8 V, respectively. The authors identify the threshold voltage and subthreshold slope as the characteristics which require greatest improvement for their devices. The threshold voltage can be shifted towards 0 V by increasing the nitrogen content in the SiON layer or reducing oxygen deciency in the ZTO layer. The subthreshold slope is degraded by excess carriers (as indicated from capacitance-voltage characteristics) and thus, can be improved by reducing oxygen deciency in the ZTO layer. Sol-gel methods for deposition of zinc tin oxide was studied by Jeong et al. . [122] These sol-gel deposited devices required a 500 C anneal to fabricate working TFTs. At processing temperatures below 500 C, no eld modulation is observed in the devices. Optimal devices were fabricated with 30 molar percent of tin, exhibiting mobilities of 1 cm2 V1 s1 and turn-on voltage of -2 V.

2.2.2.4 TFTs with multicomponent oxide layers: ZIO

Several researchers have explored various stoichiometries of zinc indium oxide (ZIO) by rf sputtering for TFTs. [14, 123, 124, 125] ZIO TFTs typically exhibit high channel mobilities (up to 40 cm2 V1 s1 ), but suffer from the same issue as In2 O3 and SnO2 , namely difculty in suppressing the carrier concentration. As a result, many of the reported ZIO TFTs are normally on devices (ID > 0 at VGS = 0 V), i.e., depletion-mode

24 devices. It is important to note that VT is commonly reported and is thus used here for comparison, but in many cases, signicant current still ows below VT . An alternative gure-of-merit, the turn-on voltage, is discussed in Sec. 3.4.2. The initial report of ZIO-based (Zn2 In2 O5 ) TFTs employed a staggered bottomgate structure with an ALD Al2 O3 -TiO2 superlattice as the gate insulator. [14] Two types of TFTs were reported, those which were subjected to a post-deposition anneal (300 and 600 C) and room temperature TFTs. TFTs subjected to a 300 C (600 C) exhibit a channel mobility and VT in the ranges of 1030 cm2 V1 s1 (4555 cm2 V1 s1 ) and 010 V (-20 to -10 V), respectively. The authors contend that the positive values of VT observed in devices annealed at 300 C are a consequence of deep traps present in the channel and/or at the interface (which must be lled by application of a positive gate voltage). TFTs not subjected to a post-deposition anneal exhibit a channel mobility of 8 cm2 V1 s1 . Barquinha et al. and Yaglioglu et al. utilize room temperature In2 O3 10 wt %ZnO (sometimes referred to as IZO) as the semiconductor layer in staggered bottom-gate TFTs. [124, 125] Barquinha et al. obtain channel mobilities approaching 40 cm2 V1 s1 while exploring the effect of semiconductor thickness (15 to 65 nm) on device performance. VT decreases with increasing semiconductor thickness (from 10 to 3 V); this effect is ascribed to reduced sheet resistance for thicker lms and a reduced effect from the back surface (opposite to insulator-semiconductor interface), where carrier trapping may be possible. Additionally, the channel mobility decreases with increasing semiconductor thickness (38 to 25 cm2 V1 s1 ); this is attributed to the longer source-drain path as the semiconductor

25 thickness is increased (recall that a staggered structure is employed). Yaglioglu et al. observe a channel mobility and VT of 20 cm2 V1 s1 and -3.2 V, respectively, for their TFTs which employ thermally grown SiO2 as the gate gate insulator. The carrier density is estimated to be 2.1 1017 cm3 using a standard van der Pauw setup. Nakanotani et al have utilized ZIO in conjunction with p-type organics to fabricate ambipolar TFTs. [126] These ambipolar devices exhibit eld effect when applying both positive and negative gate bias. Additionally, electroluminescence was observed in TFTs utilizing ZIO and tetracene, with the intensity of the luminance controlled by the gate-tosource voltage. A route towards solution deposition of ZIO has been explored by Lee et al. [127] Lee et al demonstrated that ZIO via inket printing is a viable option to realize the semiconductor layer for TFTs. These ZIO-based TFTs exhibit turn-on voltages of -25 V and mobility of 7.4 cm2 V1 s1 after processing at 600 C.

2.2.2.5 TFTs with multicomponent oxide layers: IGO

Indium gallium oxide (IGO)-based TFTs were employed in transparent integrated circuits (inverters and ring oscillators). [128] These TFTs used a 100 nm SiOx gate insulator deposited by plasma-enhanced chemical vapor deposition (PECVD) and were patterned using standard photolithography techniques. Post-deposition annealing at 500 C resulted in TFTs with a channel mobility and turn-on voltage (discussed in Sec.3.4.2) of 7 cm2 V1 s1 and 2 V, respectively. The maximum oscillation frequency of the ring oscillator circuit is 9.5 kHz (with 80 V supply voltage). The rather low oscillation

26 frequency is due to loading from large parasitic capacitances associated with each TFT (142 nF/cm, 200 m source/gate and drain/gate overlap). .

2.2.2.6 TFTs with multicomponent oxide layers: IGZO

Indium gallium zinc oxide (IGZO)-based TFTs have been fabricated by PLD and rf sputtering. [129, 10, 16, 130, 131] The initial IGZO-based (InGaO3 (ZnO)5 ) TFTs employed single crystalline IGZO layers, with indium oxide layers alternating with gallium zinc oxide layer, which were obtained through the use of a high temperature anneal and yttria-stabilized zirconia substrates. [129] These TFTs employ a coplanar top-gate structure with a 80 nm thick HfO2 gate insulator. The channel mobility, VT , and ID 80 cm2 V1 s1 , 3 V, and 106 , respectively. Yabuta et al. explored amorphous IGZO-based (InGaZnO4 ) TFTs with a staggered top-gate structure. [130] rf sputtering is used for deposition of the semiconductor and insulator (Y2 O3 ) layers. While no intentional substrate heating is used, the maximum processing temperature is 140 C due to heating from the sputtering process during insulator deposition. The channel mobility, VT , and ID 108 , respectively. Iwasaki et al. explored the IGZO phase space for TFTs (which utilize a staggered bottom-gate structure) using a combinatorial approach with rf co-sputtering from three cathodes. With this experimental setup, the range of compositional variation is 1070% for each material. [131] Iwasaki et al. indicate that the optimal O2 partial pressure employed during deposition changes for different stoichiometries. A lower O2 partial presono f f ono f f

are

are 12 cm2 V1 s1 , 1 V, and

27 sure is required to produce functioning TFTs (i.e., TFTs that switch from well-dened on to off regions) when the Ga content of lms increases. In contrast, a higher O2 partial pressure is required to produce functioning TFTs when the In content of lms increases. In:Ga:Zn ratios of 37:13:50 resulted in the best performance, where the channel mobility, VT , and ID
ono f f

are 12 cm2 V1 s1 , 3 V, and 107 , respectively.

Park et al. have formed TFTs via a self-aligned process. [132] In this process a topgate device is realized with 100 nm of CVD grown silicon dioxide as the gate insulator. After patterning of the gate electrode and gate dielectric, the device is exposed to an argon plasma, which dopes the exposed semiconductor region with oxygen vacancies, rendering them conductive. These conductive semiconductor regions constitute the source and drain regions. All processing is accomplished below 200 C. Park et al. have also studied the affects of water on IGZO-based TFTs. [133] Two competing effects are analyzed, for lm thicker than 100 nm, water appears to act as an electron donor, manifesting as a large negative threshold voltage shift. For lms thinner than 70 nm, water appears to act as an acceptor-like trap, manifesting as a large increase in subthreshold swing characteristics. The mechanism for both electron donor and acceptorlike trap appears to both be reversible. Song et al. examine the short-channel effects of IGZO based TFTs. [21] IGZObased TFTs with source-to-drain separation of 50 nm are fabricated utilizing e-beam lithography. IGZO-based TFTs for this study were built on silicon nitride and the TFT stack is annealed in a nitrogen ambient at 300 C. These devices showed INC of 8.2 cm2 V1 s1 and VON of -2 V. Varying the source-to-drain separation from 50 nm to 500

28 nm had minimal effects on the subthreshold swing and turn-on voltage. The drain current however did not scale linearly with source-to-drain separation, and is attributed to the effect of contact resistance. Kim et al. have demonstrated a passivated IGZO TFT, utilizing a CVD silicon dioxide as the passivation layer. The TFT stack prior to source and drain deposition but including the passivation layer is annealed at 350 C. Devices with the passivation layer exhibited a INC of 36 cm2 V1 s1 and a VON of 0 V, however devices without the passivation layer showed reduced performance due to damage during the source and drain patterning. Flexible IGZO-based TFTs (InGaZnO4 ) on 200 m thick polyethylene terephthalate using a coplanar top-gate structure have been demonstrated by Nomura et al. [16] All layers were deposited by PLD at room temperature, including the Y2 O3 gate insulator. The channel mobility, VT , and ID
ono f f

are 8 cm2 V1 s1 , 1.6 V, and 103 , respectively.

TFT characteristics were not signicantly altered by bending. Additionally, the TFT is stable up to 120 C. IGZO-based integrated circuits (inverters and ring oscillators) were demonstrated by Ofugi et al. [10] The gate length of these TFTs was 10 m. Additionally, these TFTs used a 100 nm SiOx gate insulator deposited by rf sputtering and were patterned using standard photolithography techniques. Discrete TFTs fabricated alongside the integrated circuits exhibited a channel mobility and threshold voltage of 3 cm2 V1 s1 and 7 V, respectively. The maximum oscillation frequency of the ring oscillator circuit is 21.5 kHz (with 18 V supply voltage).

29 IGZO-based TFTs have also been utilized in an electronic paper demonstration. [134] Ito et al. report on the fabrication IGZO-based TFT array on glass with an electrophoretic display. The 4 in panel has a resolution of 200 pixels per inch and a pixel count of 640 480. Discrete TFTs exhibited a INC of 2.8 cm2 V1 s1 and VON of 2 V.

2.3

Conclusions
This chapter provides a summary of electrical and optical properties for several n-

type TCO semiconductors. The properties of ZTO, IGO, and IGZO are reviewed in more detail, as these materials are of primary interest for this research. Finally, a summary of oxide semiconductor-based TFTs is given, including discrete device performance and examples of integration.

30

3. TFT FABRICATION AND CHARACTERIZATION

This chapter presents information regarding the fabrication and characterization of TFTs and TTFTs. First, deposition techniques used in TFT and TTFT fabrication are discussed. Second, electrical characterization of TFTs is discussed.

3.1 Thin-lm deposition and processing

This section covers deposition and processing techniques that are used for this research. Many other processing techniques are available, as explained in detail elsewhere. [135]

3.1.1 Evaporation
Evaporation is a deposition technique whereby the material to be deposited begins as a solid, goes into a vapor phase, and then recondenses back to a solid thin lm. [135] The transition from solid to vapor can either be direct, referred to as sublimation, or indirect via a transition from a solid to a liquid phase, i.e., melting, and subsequently from a liquid to a vapor phase, i.e., vaporization. Whether the material sublimes or melts and vaporizes depends on the heating source, and the material to be deposited. Additionally the temperature at which the source material sublimes or vaporizes depends strongly on the composition of the source material. Note that the stoichiometry of the growing lm may be different from the source material, such as oxides which tend to be reduced during evaporation.

31 Evaporation at the OSU solid state processing lab is accomplished using a small desktop evaporator manufactured by Polaron. For the research described in this thesis, the Polaron is used for deposition of aluminum. The main chamber for this system is comprised of a glass bell jar assembly. High-vacuum of 5 x 107 Torr is achieved with a diffusion pump. The heating element is a resistive element, a tungsten basket. The aluminum material is placed in the tungsten basket. A current of 30 A is passed through the tungsten basket, at which point the aluminum melts and subsequently vaporizes. In addition to thermal evaporation, an alternative method is electron beam evaporation which utilizes a high energy (5-30 keV) electron beam to heat a source material. One of the drawbacks of electron beam evaporation is possible damage to the deposited thin-lm from x-rays generated by the electron beam. Electron beam evaporation at the OSU solid state processing lab is accomplished using a custom built system. The electron beam evaporation system utilizes a stainless steel chamber which includes a thermal source for deposition of a second material concurrent with the electron beam evaporation.

3.1.2 Sputtering
Sputtering is a common thin lm deposition technique whereby a plume of the source material is created by energetic ions, generally argon ions. Sputtering is the primary deposition method utilized in this work, and is thus given more attention than other methods discussed in this thesis. In the most simple conguration, the DC diode sputtering system, an anode, which is usually grounded, and a cathode are placed within a vacuum chamber. The chamber

32 is evacuated to high vacuum to remove any impurities. The chamber is backlled with an inert gas and a DC eld on the order of 100 V/cm is applied between the electrodes. Any free electrons within the chamber are accelerated by the eld, reaching energies high enough to ionize more gas atoms upon collision. The cascading process repeats, leading to gas breakdown and the establishment of a glow discharge in the chamber. The negative electrons are swept by the eld to the positive anode while the positive ionized gas species are attracted towards the negative cathode. As the ions strike the cathode, secondary electrons are emitted from the surface; these secondary electrons allow the discharge to be sustained. Because the mass of the electrons is much smaller than that of the ions, they are quickly accelerated away from the negative cathode, leaving a positively charged region in front of the cathode. This high-eld region is known as the Crookes dark space and accounts for most of the voltage dropped between the anode and cathode. This region accelerates positively charged ions toward the cathode leading to atoms and clusters of atoms being ejected from the cathode. In sputtering, the cathode is a pellet of the source material (the target) while the substrate is placed on the anode. The atoms ejected from the cathode recondense onto the anode surface. In practice, strong magnets are employed behind the cathode. The magnetic conguration is designed such that the magnetic eld causes electrons to gyrate in loops parallel to and conned near the cathode surface, greatly increasing the chance of ionization. This allows operation at lower pressures than with non-magnetron congurations. The disad-

33 vantage of a magnetron conguration is preferential erosion in certain areas, leading to material waste and non-uniform deposition. Additionally, DC congurations are only possible when the target is made of a conducting material, such as a metal, which can source secondary electrons continuously to sustain the glow discharge. For non-conductors, an AC eld is used, typically created by an rf generator at 13.56 MHz. The applied AC excitation creates a self-biased DC voltage localized in front of the cathode, leading to sputtering as in a DC conguration. During the short positive portion of the excitation, electrons are attracted towards the target to replenish lost secondary electrons. Reactive sputtering can be employed by owing a reactive gas in combination with an inert gas during the sputter deposition process. For example, when sputtering an oxide from a metal or ceramic target, oxygen is introduced into the chamber in a controlled manner to adjust lm properties. At the OSU solid state processing lab, sputtering is performed using a custom built sputtering system denoted the Tasker/Chiang (Tang) sputtering system. [136, 137] The Tang is a cylindrical, stainless-steel, load-locked chamber. [136] High-vacuum is achieved using a turbomolecular pump. The Tang has three side-mounted 2 sputtering gun and two side-mounted 3 sputtering gun. Gas ow is controlled via four mass ow controllers which can introduce up to four different gas compositions. Currently the system is congured with argon (with a maximum ow of 100 standard cubic centimeters per second (sccm)), nitrogen (with a maximum ow of 50 sccm,) oxygen (with a maximum

34 ow of 50 sccm,) and a gas mixture of 9 parts argon to 1 part oxygen (with a maximum ow of 10 sccm.) Thin lms deposited across a 15 cm wafer using this system is shown to be good. IGZO-based thin-lm transistors were fabricated on a 15 cm wafer in conjunction with Sharp Labs. Across the 15 cm wafer, 96 TFTs were tested, exhibiting a mean AV G of 11.1 cm2 V1 s1 , with a range and standard deviation of 1.6 and 0.4 cm2 V1 s1 , respectively. Measured VON values exhibited a mean of -2.2 V, a range of 2V, and a standard deviation of 0.23 V. For this thesis, semiconductor layers and ITO contacts are deposited via sputtering.

3.1.3 Plasma-enhanced chemical vapor deposition (PECVD)

Chemical vapor deposition (CVD) techniques employ gas-phase sources (rather than solid sources as employed in PVD) to form a thin lm. [138] After the gas-phase precursors are introduced into the chamber, they are transported (by diffusion) to the substrate, where a reaction that results in thin lm formation occurs. This reaction can be driven in a variety of ways, including (but not limited to) thermally, by photons, or by glow discharge. Plasma-enhanced chemical vapor deposition (PECVD) utilizes both a glow discharge and heat to drive the thin lm-forming reaction. Use of a glow discharge allows for reduced processing temperatures compared to conventional CVD. In this work, PECVD is utilized to deposit SiO2 for use as a gate insulator. Two different gas sources are utilized: silane (SiH4 ) and TEOS(SiO4 C8 H20 ). Silane is a gaseous species consisting of hydrogrenated silicon, analogous to methane. Typically silane is

35 converted to silicon dioxide in the presence of nitrous oxide (N2 O) via

SiH4 + 4N2 O SiO2 + 4N2 + 2H2 O.

(3.1)

TEOS is an organometallic liquid consisting of a tetrahedral coordinated silicon with an ethyl ester (-O-CH2 -CH3 ) attached at each of the tetrahedral sites. TEOS is typically introduced into a deposition chamber via a carrier gas (N2 ) that is introduced into a bubbler containing TEOS. TEOS conversion to silicon dioxide consists of

SiO4C8 H20 + 12O2 SiO2 + 8CO2 + 10H2 O.

(3.2)

3.1.4 Atomic layer deposition (ALD)

Atomic layer deposition (ALD) is a powerful deposition technique that produces lms with excellent step coverage and few pin-hole defects. [139] The main difference between previously discussed thin lm deposition techniques (i.e. evaporation and sputtering) and ALD is the growth mechanism. In the previously discussed techniques, thin lm growth is dominated by nucleation, thus forming microcrystals, whereas ALD is a self-controlled process, resulting in the sequential growth of monolayers or submonolayers. Execution of the ALD process involves anionic and cationic precursor gases which are separately introduced into the deposition chamber. [140] The cationic species is rst introduced so that several monolayers are adsorbed onto the substrate surface. An inert gas then purges the surface, causing desorption of weakly bound adatoms and, ideally,

36 retention of a single saturated monolayer of lm growth. Next, an anionic species is introduced and reacts with the adsorbed cationic precursor at the substrate surface. A subsequent anion purge completes the sequence. This alternating cycle is repeated until the appropriate lm thickness is achieved. Note that saturated monolayer growth does not always occur. Additionally, the alternating ALD cycle can be appropriately modied to accomplish doping or alternate atomic engineering of the deposited layer.

3.1.5 Post-deposition thermal processing

After deposition, many lms require a thermal anneal. Annealing is accomplished by controlling the ambient pressure, ambient composition and the temperature of the substrate. During thermal annealing, thin lms can react with the processing ambient, which can consist of, for example, oxidizing or reducing gases. Thin lms can also undergo crystallization, diffusion, and a change in lm stress due to thermal annealing. For the research discussed in this thesis, Thermolyne 62700 and 47900 box furnaces are used for thermal annealing. The thermolyne box furnaces utilizes resistive coils as the heating element, a thermocouple as the temperature sensor, and room air as the annealing ambient. No vacuum pump or gases are connected to this system. Samples are placed on alumina discs during annealing to prevent contamination. In addition a Neytech Qex system is used for thermal annealing. The Neytech system is a cylindrical chamber and utilizes resistive coils and a thermocouple as the heating element and heat sensor, respectively.

37

3.2

Hall measurement
The Hall effect, discovered in 1879, can be used to determine the resistivity, carrier

type and concentration, and mobility of a sample. [141, 142] The Hall effect is based on the Lorentz force, F = q( x B ), v (3.3)

where q denotes the charge of the particle, the velocity vector, and B the magnetic v eld vector. The Lorentz force deects carriers (the direction of deection is determined by charge of the particle and the cross product of and B ) towards the top or bottom v of the sample, creating a potential known as the Hall voltage, VH . The Hall voltage is dened as, VH = BI , qtn (3.4)

where I is the current, t is the thickness of the sample and n is the carrier concentration. In addition, one can dene the Hall coefcient, RH ,

RH =

tVH . BI

(3.5)

Note that the sign of the Hall coefcient indicates dominant carrier type; a negative Hall coefcient indicates that electrons are the dominant carriers. [141, 142] After determining the Hall coefcient, the carrier concentration, n, is given by,

n=

1 . qRH

(3.6)

38 To determine the Hall mobility, the lm resistivity is rst assessed using,

t R12,34 + R23,41 . ln(2) 2

(3.7)

The two resistances in Eq. 3.7 can be generalized as Rab,cd and are measured by forcing a current from contact a to b, then measuring the voltage between terminals d and c. Finally, the Hall mobility, H , is obtained using,

H =

RH .

(3.8)

Note that the Hall mobility is related to the conductivity mobility for electrons (or holes) via H = rn(p) , where r, the scattering factor, and is dened as, (3.9)

r=

2 . 2

(3.10)

is the mean time between scattering events. r is typically between 1 and 2. Specically, r is 1.18 for lattice scattering and 1.93 for impurity scattering. [141] For measurements conducted at OSU, a symmetric lamella-type van der Pauw structure is used. [141] When using this structure, terminals to the sample should be small and close to the sample edges. Sample and contact symmetry is not required, but

39 in practice is preferred. If these conditions are not met, appropriate corrections must be made.

3.3

Thin-lm transistor fabrication

Figure 3.1 shows two TFT structures fabricated for this thesis: a fully-transparent

TTFT and a non-transparent TFT built on a silicon substrate. Both TFTs are bottom-gate staggererd TFTs, as shown in Fig. 3.3.

3.3.1 Fully-transparent TTFT

Figure 3.1a-b shows a cross section of a fully-transparent TFT. A fully-transparent TTFT is prepared on Nippon Electric Company glass substrates (NEG OA2) coated with a 100 nm sputtered indium tin oxide (ITO) gate electrode lm and a 220 nm atomic layer deposited superlattice of AlOx and TiOx (ATO). The ATO has a dielectric constant of 15. The ITO and ATO layers constitute the gate contact and insulator, respectively, of a bottom-gate TTFT. An 40 nm semiconductor layer is then deposited via RF magnetron sputtering through a shadow mask for semiconductor denition using 2 diameter sputter targets, a target-to-substrate distance of 7.5 cm, a power of 50 W, a pressure of 5 mTorr, and an Ar:O2 ratio of 9:1. Next, an 200 nm layer of ITO is deposited by RF sputtering through a shadow mask for source and drain patterning using a 3 target in pure Ar at a pressure of 30 mTorr. Aluminum deposited via thermal evaporation is used as an alternative source and drain contact material. There is no measureable difference between aluminum source/drain TTFTs and ITO source/drain TTFTs. The TFT length and width

40

I TO

(a)

I TO

Se m ic onduc t or ATO I TO

Gla ss

Al

(b)

Al

Se m ic onduc t or Silic on diox ide

Silic on Gold

Figure 3.1: TFT structures used for the research discussed in this thesis, including (a) fully-transparent thin-lm transistor and (b) non-transparent thin-lm transistor.

41 are 1520 m and 7170 m, respectively. The entire thin lm stack is then furnace annealed in air using a one hour ramp and a 10 minute hold at the processing temperature for 10 minutes; the sample is then allowed to cool inside the furnace for 5 hours to reach room temperature. Annealing occurs prior to aluminum source/drain deposition when it is utilized.

3.3.2 Non-transparent TFT

Figure 3.1a shows a cross section of a non-transparent TFT. A non-transparent TFT is prepared on heavily-doped p-type silicon substrates with 100 nm of thermal silicon dioxide and a gold back contact. Note that the heavily-doped silicon acts as both the substrate and the gate electrode. An 40 nm semiconductor layer is then deposited via RF magnetron sputtering through a shadow mask for semiconductor denition using a 2 diameter sputter target, a target-to-substrate distance of 7.5 cm, a power of 50 W, a pressure of 5 mTorr, and an Ar:O2 ratio of 9:1. Next, an 200 nm layer of aluminum is deposited via thermal evaporation to form the source and drain electrodes. Both the semiconductor layer and source/drain electrodes (ITO) are patterned through the use of shadow masks; the TFT length and width are 100 m and 1000 m, respectively. The thin lm stack is then furnace annealed similar to the fully-transparent TTFT.

3.4

Transistor overview
Figure 3.2 shows the basic structure of a TFT and several energy band diagrams

as viewed through the gate of an n-semiconductor, accumulation-mode TFT. [143] The

42 energy band diagram of Fig. 3.2b shows the device at equilibrium, with 0 V applied to the source, drain, and gate. Figure 3.2c shows an energy band diagram with the gate negatively biased. The applied negative bias repels mobile electrons from the semiconductor, leaving a depletion region near the insulator-semiconductor interface. When compared to Fig. 3.2b, this biasing condition has a reduced conductance due to the reduced number of mobile electrons in the semiconductor. Figure 3.2d shows an energy band diagram with the gate positively biased. The applied positive bias attracts mobile electrons, forming an accumulation region near the insulator-semiconductor interface. These excess mobile electrons lead to an increase in the conductance. Beginning with the case where the gate is biased positively and accumulation is established, i.e., Fig. 3.2d, consider the effect of an applied drain-source voltage, VDS . Initially the semiconductor is modeled as a resistor, i.e. linearly increasing current with VDS . As VDS increases, accumulation near the drain decreases. As VDS is increased further, the region near the drain eventually begins to deplete. The voltage at which the semiconductor region near the drain is fully depleted of carriers is denoted the pinchoff voltage. Therefore, application of VDS greater than the pinch-off voltage results in a saturated drain current characteristic. TFT device structures can differ from that shown in Fig. 3.2a. Four possible TFT device structures are shown in Fig. 3.3. [144] As evident from Fig. 3.3, devices can be either staggered or coplanar. In a coplanar conguration, as shown in Figs. 3.3b and 3.3d, the source and drain contacts and the insulator are on the same side of the semiconductor. In such an arrangement, the source-drain contacts are in direct contact with the induced

43

Sourc e (a)

Dra in

Conduc t or Se m ic onduc t or Die le c t ric

Gat e
VGS = 0 V VGS < 0 V VGS > 0 V

Insulator

(d)

Ins sulator

M Metal

S Semiconducto or

Meta al

(c)

Figure 3.2: (a)The basic structure of a TFT and corresponding energy band diagrams as viewed through the gate for several biasing conditions: (b) equilibrium, (c) VGS <0 V, and (d) VGS >0 V

Semicon nductor

Metal

(b)

Semic conductor

Insulator

44

Sourc e

Dra in Gat e

Sourc e

Gat e

Dra in

(a) (b) Sourc e Dra in

Conduc t or Se m ic onduc t or Die le c t ric

(c) (d) Gat e Dra in

Gat e

Sourc e

Figure 3.3: Four general thin-lm transistor congurations, including: (a) staggered bottom-gate, (b) coplanar bottom-gate, (c) staggered top-gate, and (d) coplanar top-gate.

45 channel. In a staggered conguration, as shown in Figs. 3.3a and 3.3c, the source and drain contacts are on the opposite side of the semiconductor from the insulator; thus, there is no direct connection to the induced channel. However, the contact area is very large when a staggered structure is used. In addition to coplanar and staggered congurations, TFTs can be classied as either bottom-gate or top-gate devices. A bottom-gate TFT, which is sometimes referred to as an inverted TFT, has the gate insulator and gate electrode located beneath the semiconductor, as shown in Figs. 3.3a and 3.3b. The top surface of a bottom-gate TFT is exposed to air or is passivated by coating the top surface with a protective layer. A top-gate TFT, as shown in Figs. 3.3c and 3.3d, has the gate and insulator located on top of the semiconductor. In a top-gate device, the semiconductor is covered by a gate insulator so that the top surface is inherently passivated. Process integration-related issues can also motivate the use of different structures. In the co-planar top-gate structure, the semiconductor is deposited rst. Therefore, the maximum semiconductor processing temperature is limited only by the semiconductor and the substrate. Notice that in both bottom-gate structures, the insulator is deposited rst. If the insulator is deposited using a glow discharge process, such as rf sputtering or plasma-enhanced chemical vapor deposition, the plasma-induced damage to the semiconductor layer can possibly be reduced using this structure (since insulator deposition typically requires the use of a higher power as compared to deposition of other layers). The co-planar structure is difcult to realize in some technologies, such as a-Si:H. aSi:H TFTs utilize ion implantation to form an ohmic contact to the semiconductor. Since

46 the maximum processing temperature of a-Si:H transistors is 350 C, damage from implantation cannot be remedied. This implies that the semiconductor must be protected during implantation. If the insulator is used as an implant-block, there is no source/drainto-gate overlap. Without this overlap, the series resistance increases and retards carrier injection. [145]

3.5

Thin-lm transistor device characteristics

This section discusses several important TFT gures-of-merit, threshold voltage

and mobility, and their estimation from experimental data.

3.5.1 DC current-voltage measurements

DC current-voltage characteristics presented in this thesis are obtained using an Agilent 4156B Semiconductor Parameter Analyzer. Measurements are executed in the dark, with a hold time of 500 ms, a delay time of 200 ms, and medium integration time. Devices are contacted using a Micromanipulator 6000 series probe station. Figure 3.4 shows an abbreviated version of the output voltage as a function of time for a typical transfer current-voltage measurement . For this measurement, VS and VD are constant values of 0 V and 1 V, respectively. VG is varied from 0 V to 4 V. At t = 0 s, the measurement begins by application of all initial voltages. VS is grounded, VD = 1 V, and VG = 0 V. These voltages are applied for 500 ms, equating to the hold time, and an additional 200 ms, equating to the rst delay time, for a total of 700 ms. At t = 700 ms the drain current, source current and gate current are measured. After

47

Time (s)

Figure 3.4: Simplied timing diagram illustrating the applied voltage to the transistor as a function of time. the measurements, the second set of voltages is applied (VS = 0 V, VD = 1 V, and VG = 1 V), held for 200 ms (equating to the second delay time) and the measurements are taken. The process of incrementing the voltage, waiting for the delay time, and taking the measurement repeats until a maximum voltage of VG = 4 V is achieved. At the maximum voltage point the voltage is applied for 200 ms, the measurement is taken, another delay period occurs and another measurement is taken prior to the gate voltage decreasing down to 3 V . The process of decrementing the voltage, waiting for the delay time, and taking the measurements continues until VG reaches 0 V.

4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5

VD

Applied Voltage (V) V

VS Hold Time Delay Time T

VG

48

3.5.2 Threshold voltage and turn-on voltage

Threshold voltage, VT , is an important TFT parameter indicative of the onset of drain current. [146] Unfortunately, it is not possible to uniquely dene VT , which sometimes leads to ambiguous or even misleading conclusions. Thus, an alternative gure-ofmerit for the onset of drain current, the turn-on voltage, is introduced at the end of this section and is extensively employed in this thesis. VT may be estimated graphically by plotting the TFT output conductance, gD , as a function of the gate-source voltage, VGS . [146] Using the square-law model of a TFT, [147] ID is given by W ID = CI L
2 VDS VDS (VGS VT ) , 2

(3.11)

where W is the width of the semiconductor, L is the length from source to drain, is the mobility in the semiconductor, CI is the gate insulator capacitance density, VDS is the drain-source voltage, and VGS is the gate-source voltage. Evaluating gD as the derivative of ID with respect to VDS leads to ID W gD = = CI (VGS VT VDS ) . VDS VGS =constant L

(3.12)

Notice that gD is directly proportional to VGS , and thus, is linear with respect to VGS . Also note that gD approaches zero as VGS approaches VT + VDS . Thus, a gD -VGS plot should be linear and an extrapolation of the linear portion of this curve to the VGS -axis is equal to VT + VDS .

49

250 200 150

gD ( S)

100 50 0

VT + VDS
0.0 10.0 20.0 30.0 40.0

-10.0 -50

VGS (V)

Figure 3.5: Output conductance-gate-to-source voltage (gD -VGS ) characteristic illustrating threshold voltage estimation via extrapolation of the linear portion of this curve to the VGS -axis intercept for an indium gallium zinc oxide semiconductor layer TFT with a width-to-length ratio of 10:1. gD is assessed at VDS = 1 V.

50 Figure 3.5 shows a gD -VGS curve for a TFT with an indium gallium zinc oxide semiconductor layer. For VGS > 25 V, the curve is linear. Using linear extrapolation of this curve to the VGS -axis intercept yields a value of 13 V. Since this plot is taken at VDS = 1 V, VT is estimated to be 12 V for this device. An alternative procedure for assessing the initiation of current ow in a TFT is to employ a log(ID )-VGS curve and to dene a turn-on voltage, VON , as the voltage at which ID begins to increase with increasing VGS . [148] This denition of turn-on voltage corresponds to the applied gate bias at which an appreciable density of mobile carriers are present within the semiconductor. Figure 3.6 shows a log(ID )-VGS plot for the same TFT as shown in Fig. 3.5. VON for this device is 2 V. It is evident from Fig. 3.6 that VON is a more accurate indicator of the onset of current than VT . Thus, for the research reported in this thesis, VON is preferred to VT as a TFT parameter.

3.5.3 Mobility
Along with threshold voltage, mobility is the other key gure-of-merit for TFTs. Mobility is a measure of the mobile carrier transport in the semiconductor and thus relates information about the current drive of the TFT. A higher mobility corresponds to a higher current drive. Four types of mobility are considered in this thesis: average mobility (AV G ), incremental mobility (INC ), saturation mobility (SAT ), and saturation-average mobility(SAT AV G . [148, 146]

51

1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E 06 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 -10.0 0.0

ID (A)

VT

VON
10.0 20.0 30.0 40.0

VGS (V)

Figure 3.6: Log(ID -VGS ) transfer characteristics showing the turn-on voltage, VON , and the threshold voltage, VT for the same device as shown in Fig. 3.5. The TFT is measured at VDS = 1 V.

52 Average mobility (AV G ) is an estimate of the mobility of all carriers induced into the semiconductor by an applied gate bias, VGS . [148] Average mobility is calculated using AV G (VGS ) = GLIN (VGS ) D , W CI (VGS VON ) L (3.13)

where W and L are the width and length of the TFT, and CI is the gate insulator capacitance, and GLIN is the output conductance as a function of applied gate bias calculated in D the linear regime, as indicated by the notation LIN , such that the TFT can be modeled as a resistor. The output conductance is also evaluated at small values of VDS and is calculated as [148]

ID (VGS ) GLIN (VGS ) = . D VDS VDS 0

(3.14)

Incremental mobility is the mobility of charges incrementally added to the semiconductor by a corresponding incremental change in VGS . [148] Incremental mobility is calculated as [148] GLIN (VGS ) D INC (VGS ) = , W CI VDS 0 L

(3.15)

where GLIN (VGS )is the change in output conductance due to a corresponding change to D VGS . This is evaluated as as GLIN D (VGS ) = . VGS VDS 0

GLIN D

(3.16)

Comparing these two mobility estimates, average mobility is of greater practical signicance, as it estimates the mobility of all carriers in the semiconductor and is more

53 useful for quantifying device performance. On the other hand, incremental mobility is of greater physical signicance, as it estimates the mobility of incrementally induced carriers with changing gate voltage and is more useful for analyzing trapping and interfacial scattering physics of carriers transiting along the semiconductor. A third mobility, saturation mobility, is extracted from a ID -VGS curve, measured with the device held in saturation. [146] Saturation mobility is calculated as 2m2 =W L CI VDS >>VGS VON

SAT

(3.17)

where m is the slope of a plot of

ID,SAT against (VGS - VT .) This slope is evaluated as ID,SAT VGS

m=

(3.18)

This SAT equation is based on the assumption that the TFT characteristics follow the ideal square-law model. This is not the case, however, for many situations. The procedure that is used for deriving SAT is not exact, but actually involves an approximation in its derivation. This can be conrmed using the conductance integral equation to derive IDSAT . Substituting in the conductance equation using the charge sheet model,

GLIN (VGS ) = D

W CI (VGS ) (VGS VON ), L

(3.19)

54 into the saturation regime form of the conductance integral equation,

IDSAT (VGS ) =

VGS VON

GLIN (VGS )dVGS , D

(3.20)

leads to IDSAT (VGS ) = W CI L

VGS VON

(VGS ) (VGS VON )dVGS .

(3.21)

Evaluating the integral in equation 3.21 via integration-by-parts results in

IDSAT (VGS ) =

W 2L CI

(VGS ) (VGS VON )2

VGS VON

W CI L

(VGS VON )2

(VGS ) dVGS , VGS

(3.22)

This is a more precise specication of IDSAT . Deriving the mobility expression for SAT from the square-law equation requires assuming that the mobility in saturation is a constant, independent of VGS , so that the integral term in equation 3.22 may be neglected. A new type of mobility, denoted as the satuation-average mobility, SAT AV G , is introduced. Its derivation is as follows. Beginning with the conductance integral equation [149], ID =
VGS VGD

GLIN (VGS )dVGS , D

(3.23)

where ID is the drain current, VGS is the gate-to-source voltage, VGD is the gate-to-drain voltage, and GLIN (VGS ) is the output conductance when the device is operated in the D linear regime (i.e., VD VS 0 V) as a function of applied gate voltage (VGS ). GLIN is D

55 evaluated as ID (VGS ) GLIN (VGS ) = . D VDS VDS 0

(3.24)

First note that when the device is in saturation, VGD is replaced by VON and the conductance integral equation is written as

IDSAT (VGS ) =

VGS VON

GLIN (VGS )dVGS . D

(3.25)

Differentiating both sides with respect to VGS yields

IDSAT = GLIN (VGS ). D VGS From the charge sheet model [148], GLIN is given as D W CI (VGS VON ). L

(3.26)

GLIN (VGS ) = D

(3.27)

Replacing GLIN in Eq. 3.26 with 3.27, noting that D IDSAT , VGS

gSAT (VGS ) = m

(3.28)

where gSAT is the transconductance of the TFT in saturation, and solving for yields m gSAT m . W CI (VGS VON ) L

SAT AV G =

(3.29)

56

20 18 16 14 12 10 8 6 4 2 0 0 .0 1 0 .0 2 0 .0 3 0 .0

(cm2V-1s-1) m

VGS (V)

Figure 3.7: Extracted average mobility (middle-black,) saturation mobility (top-dark gray,) and saturation-average mobility (bottom-light gray) characteristics for a single IGZO-based thin-lm transistor.

57 Figure 3.7 shows three types of calculated mobility values for a single IGZO-based TFT. The black curve (middle curve) is an average mobility calculated from data taken with VDS = 1 V. The dark gray curve (top curve) is a saturation mobility calculated using Eq. 3.7 from data taken with VDS = 30 V. The light gray curve (bottom curve) is the saturation-average mobility calculated using Eq. 3.15 from the same data as the saturation mobility. At VGS = 30 V, the saturation mobility (17 cm2 V1 s1 ) overestimates the mobility by 20%, when compared to the average mobility (13 cm2 V1 s1 ). The saturation-average mobility (12.7 cm2 V1 s1 ) is clearly a more accurate estimate of mobility, underestimating the mobility by only 3% when compared to the average mobility.

3.5.4 Drain current swing and drain current on-to-off ratio

The subthreshold swing (S) and the drain current on-to-off ratio (IONOFF ) are D estimated using a semi-log plot of the transfer characteristics taken at high VDS (i.e. VDS > VDSAT = VGS - VON ,) as shown in Fig. 3.8, S is the inverse of the maximum slope in the transfer characteristic, S= log10 (ID ) 1 . VGS max

(3.30)

S is a useful quantication of how efciently the device turns on and is typically less than 1 V/decade. For the device shown in Fig 3.8, S500 mV/decade. Drain current on-to-off ratio (IONOFF ) is a parameter for switching application D and provides a useful measure of device performance. IONOFF is simply the on-current D

58

1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E 06 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 -10.0 0.0

ID (A)

S
10.0 20.0 30.0 40.0

VGS (V)

Figure 3.8: Log(ID -VGS ) transfer characteristics showing the drain current swing, S, and the drain current on-to-off ratio, IONOFF for the same device as shown in Fig. 3.5. The D TFT is measured at VDS = 30 V. divided by the off-current,
ONOFF ID = ON ID OFF ID

OFF IDON-O

(3.31)

For the device shown in Fig 3.8, IONOFF 108 . D

3.6

Conclusions
A summary of thin lm processing techniques relevant to the fabrication of TFTs

for this thesis is presented. Thin lm processing techniques explored include evaporation, sputtering, chemical vapor deposition, atomic layer deposition, and post-deposition

59 annealing. Sputtering is discussed in some detail, as these techniques have been essential to the development of TFTs presented in Chapter 4. The Hall measurement is discussed as a method of evaluating mobility, carrier concentration, and conductivity of thin-lms. Finally TFT characterization techniques are discussed including several key metrics: turn-on voltage, subthreshold voltage swing and TFT mobility.

60

4. REACTIVE SPUTTERING OF OXIDE SEMICONDUCTORS

Reactive sputtering using a metallic target has several advantages compared to deposition methods in which a ceramic target is used. [135, 150] Reactive sputtering using a metallic target usually results in a higher deposition rate. The physical properties of the metal lead to a more durable target of higher purity and superior thermal conductivity. Finally, a metallic target is easier to fabricate, requiring less care and cost than is involved in the fabrication of a ceramic target.

4.1 Introduction
Zinc oxide-based and zinc tin oxide-based thin-lm transistors are fabricated via reactive rf magnetron sputtering using metallic targets. The oxygen ow rate is found to be an important process parameter for low-temperature zinc oxide and zinc tin oxide synthesis. Sputtering using a low oxygen ow rate yields highly conductive metallic lms, whereas a high oxygen ow rate results in transistors with poor mobility. Zinc oxide-based thin-lm transistors fabricated at an optimal oxygen ow rate near room temperature, i.e. without intentional substrate heating, exhibit incremental mobilities of 5 cm2 V1 s1 , turn-on voltages of -10 V, and drain current on-to-off ratios of 106 . Post-deposition annealing of these lms at 300 C and 600 C yields transistors with incremental mobilities up to 7 and 10 cm2 V1 s1 , respectively. Figure 4.1 shows the cross section and plan view of a typical bottom-gate TFT. TFTs are prepared on heavily doped p-type silicon substrates with 100 nm of thermal

61 silicon dioxide and a tantalum/gold back contact. An 50 nm zinc oxide layer is then deposited via rf magnetron sputtering through a shadow mask for semiconductor denition using a 2 diameter zinc metal sputter target purchased from Cerac, Inc. A target-tosubstrate distance of 7.5 cm, a power of 50 W, and a pressure of 30 mTorr is used during the zinc oxide deposition. Gas ow for the sputtering ambient is controlled via two MKS mass ow controllers. 25 sccm of argon and various oxygen ow rates are introduced into the chamber, and then the chamber pressure is adjusted to 30 mTorr. After the semiconductor deposition, an 100 nm layer of aluminum is deposited by thermal evaporation to form source/drain electrodes which are patterned through the use of shadow masks. The TFT device length and width are 200 m and 2000 m, respectively. Post-deposition annealing is accomplished in a Thermolyne 47900 box furnace. Samples are annealed at temperature for 1 hour.

4.2

Reactive Zinc Oxide

Zinc oxide is a wide band gap semiconductor employed in numerous applications.

[151, 152, 153, 154, 155, 150] The piezoelectric nature of zinc oxide lends itself to surface acoustic wave device and optical waveguide applications. [151, 152] Zinc oxides large band gap and photoelectric properties leads to its use in UV lters and detectors. [153] Zinc oxide is also used as a transparent conductor because of its optical and electrical properties. [154, 155, 150] Recently, zinc oxide has been utilized as the semiconductor layer in thin-lm transistors (TFTs). Hoffman et al. reported fully transparent TFTs utilizing ion-beam sput-

62

Al

Al Al 200 mm Al

ZnO (50 nm) SiO2 (100 nm)

2000 mm

Si Au/Ta

Figure 4.1: Cross sectional and plan view of a typical bottom-gate TFT.

ZnO

63

1.2 1.0

ID (mA)

0.8 0.6 0.4 0.2 0.00 5 10 15 20 25 30 35 40

VDS (V)
Figure 4.2: Drain current-drain voltage (ID -VDS ) characteristics of a zinc oxide TFT which is fabricated near room temperature, i.e., without intentional substrate heating. VGS is decreased from 40 V (top curve, showing maximum current) to 0 V in 10 V steps. tering of zinc oxide. [156] Carcia et al. fabricated zinc oxide-based TFTs on both silicon substrates and plastic substrates. [9, 157] Masuda et al. demonstrated TFTs using pulsed laser deposited zinc oxide. [11] All previously reported zinc oxide-based TFTs utilized ceramic targets. This section discusses the fabrication of zinc oxide-based TFTs via reactive rf sputtering using a metallic zinc target in an argon/oxygen ambient. Figure 4.2 shows the drain current-drain voltage (ID -VDS ) characteristics of a zinc oxide TFT processed near room temperature, i.e. without intentional substrate heating, using an oxygen ow of 0.5 sccm. The gate-to-source voltage, VGS , is decreased from

64

6 5

minc (cm2V-1s-1)

4 3 2 1 0 -20

-10

10

20

30

40

VGS (V)

Figure 4.3: Incremental mobility-gate voltage characteristics of a zinc oxide TFT which is fabricated near room temperature, i.e., without intentional substrate heating. 40 V (top curve) to 0 V in 10 V increments. This TFT exhibits qualitatively ideal characteristics, including hard drain current saturation. Notice also that the spacing between each ID -VDS curve is large, which is indicative of an appreciable induced-channel carrier mobility. Turn-on voltage and drain-current on-to-off ratio for this device are -10 V and 106 , respectively. Figure 4.3 shows the incremental mobility-VGS characteristics for the device shown in Fig. 4.2. Notice that the incremental mobility is strongly dependent upon VGS , consistent with trends reported by Hoffman et al. and Nishii et al. [148, 158] On the mo-

65 bility scale used, the mobility increases at VGS 15 V, and continues to increase to 5.5

cm2 V1 s1 at VGS = 40 V. Thus, an overvoltage of approximately 50 V with respect to the turn-on voltage, or 40 V with respect to the threshold voltage (estimated as 0 V from Fig. 4.2), is required in order to obtain an incremental mobility of 5.5 cm2 V1 s1 . Furthermore, Fig. 4.3 provides no evidence of a saturation in the incremental mobility with increasing VGS . Thus, a further increase in VGS would result in an even higher incremental mobility. This strong dependence of incremental mobility on VGS and lack of mobility saturation with respect to increasing VGS is ascribed to grain boundary trapping and grain boundary energy barrier-inhibited electron transport. [148, 158, 159] Note that reported mobility values in this paper are measured an overvoltage of 50 V with respect to turn-on voltage. In-situ substrate heating and post-deposition annealing increases the incremental mobility slightly. A substrate temperature of 300 C yields transistors with peak incremental mobilities of 6.5 cm2 V1 s1 . Post-deposition annealing at 300 C and 600
C

yields transistors with incremental mobilities of 7 and 10 cm2 V1 s1 , respectively.

Turn-on voltages for all of the thermally processed devices are -4 V. Improvements in incremental mobility due to thermal processing are ascribed to improved crystallinity, measured via XRD. The oxygen ow rate is the most important process parameter for determining the mobility performance of a zinc oxide TFT. Mobilities of transistors fabricated at room temperature, with substrate heating, and with post-deposition annealing all show signicant dependence on the oxygen ow rate.

66 For devices processed near room temperature, the window for optimal oxygen ow is between 0.5 sccm and 1 sccm. Sputtering in an ambient with an oxygen ow 0.4

sccm, results in a highly conductive lm. The highly conductive nature of the lm is attributed to the incorporation of metallic zinc into the lm. A sputtering ambient with an oxygen ow 1 sccm yields a lms with a low incremental mobility.

For a TFT processed at a substrate temperature of 300 C, the optimal oxygen ow is 1.25 sccm. Increasing the oxygen ow above 1.25 sccm results in a drastically smaller mobility. For TFTs processed with a post-deposition anneal at 600 C, the optimal oxygen ow is again 1.25 sccm. These devices yield peak incremental mobilities of 10 cm2 V1 s1 . Increasing the oxygen ow to 2.5 sccm yields reduced peak incremental mobilities of 3 cm2 V1 s1 . The decrease in mobility with increasing oxygen partial pressure is attributed to a reduced density of oxygen vacancies, which in turn leads to an increase in the barrier height at grain boundaries and a diminished carrier mobility. [157, 159] For 600
C

annealed TFTs, the diminished carrier mobility is concomitant with an increase in

the turn-on voltage, -10 V and -2 V for oxygen ow rates of 1.25 sccm and 2.5 sccm, respectively, as is to be expected with a decrease in the oxygen vacancy concentration. Carcia et al. report a similar trend of decreasing mobility with increasing oxygen partial pressure. [157] However, the optimal oxygen percentage that is reported by Carcia et al., 0.05%, is signicantly lower than the optimal oxygen percentage we obtain for reactive sputtering, 1.67%. This dramatic difference in optimal oxygen percentage is

67 due to two key differences in the zinc oxide deposition procedure: the use of a ceramic target versus a metallic target, and the use of a low power density versus a relatively high power density. The ceramic target used by Carcia et al. contains a stoichiometric ratio of oxygen to zinc. Thus, a small amount of additional oxygen incorporated into the growing lm compensates for oxygen loss during sputtering. In reactive sputtering, all of the oxygen in the growing lm originates from the sputtering ambient, necessitating the use of a larger oxygen percentage. In addition, Carcia et al. utilize a low power density, 0.30.5 W/cm2 , during sputtering to minimize damage to the growing lm. This low power density results in a low deposition rate so that a lower oxygen pressure is required to fully oxidize this slowly growing lm. This is in direct contrast to our reactive sputtering at a higher power density, 2.5 W/cm2 , which necessitates the use of a much higher oxygen ow rate in order to supply enough oxygen to ensure that the zinc oxide lms are fully oxidized.

4.3

Reactive Zinc Tin Oxide

Zinc tin oxide is a wide band gap semiconductor employed primarily as a transpar-

ent conductor and as a semiconductor layer for thin-lm transistors(TFTs.) [160, 161, 162, 163, 164, 165, 166] Previous work with zinc tin oxide as a semiconductor layer for TFTs focused on sputtering from a ceramic target. This section discusses the fabrication of zinc tin oxide-based TFTs via reactive sputtering using a metallic zinc/tin target in an argon/oxygen ambient.

68 Similarly to the zinc oxide TFTs, zinc tin oxide TFTs are prepared on heavily doped p-type silicon substrates with 100 nm of thermal silicon dioxide and a tantalum/gold back contact. An 50 nm zinc tin oxide layer is then deposited via magnetron sputtering through a shadow mask for semiconductor denition using a 2 diameter 2:1, zinc:tin metal sputter target purchased from Kamis Inc. A target-to-substrate distance of 7.5 cm, a power of 50 W, and a pressure of 30 mTorr is used during the zinc tin oxide deposition. Gas ow for the sputtering ambient is controlled via two MKS mass ow controllers. 25 sccm of argon and various oxygen ow rates are introduced into the chamber, and then the chamber pressure is adjusted to 30 mTorr. The target preparation before deposition of the semiconductor layer consists of two steps. The zinc/tin target is rst sputtered in pure argon for 20 minutes to remove the target surface oxide layer. Next the zinc/tin target is sputtered in the processing ambient for 20 minutes to simulate equilibrium conditions at the target surface. After the semiconductor deposition, an 100 nm layer of aluminum is deposited by thermal evaporation to form source/drain electrodes which are patterned through the use of shadow masks. The TFT device length and width are 200 m and 2000 m, respectively. Semiconductor layer annealing is accomplished in a Thermolyne 47900 box furnace. Samples are annealed at temperature for 1 hour. Log(ID )VGS characteristics (at VDS = 40 V) are shown in Fig. 4.4 for zinc tin oxide TFTs which are subjected to a 300 C and 500 C semiconductor layer anneal. Note that ID , VGS , and VDS are the drain current, gate-to-source voltage, and drain-to-source voltage, respectively. The inverse subthreshold slope for both devices are 500 mV/decade.

69

10-2 10 10 10 10 10 10 10 10
-3 -4 -5 -6 -7 -8

500 C 300 C
o

ID (A)

10-9
-10 -11

-5

15

25

35

VGS (V)
Figure 4.4: Log(ID )VGS characteristics obtained at VDS = 40 V for two zinc tin oxide TFTs fabricated via reactive rf sputtering which are subjected to a 300 C and 500 C post-deposition anneal.

70 Electrical parameters often used to characterize a TFT are turn-on voltage, drain current on-to-off ratio, and semiconductor mobility. The turn-on voltage, Von , is the gate voltage at the onset of semiconductor conduction, i.e., the gate voltage at the onset of the initial sharp increase in current in a log(ID )VGS characteristic. [148] Von is equal to -2 V and 2 V for the devices shown in Fig. 4.4. The ID on-to-off ratio is 107 . Note that the transistor off current is established by gate leakage, which is typically 1011 to 109 A for the SiO2 gate dielectric and device dimensions employed here. Carrier mobility is arguably the most important TFT electrical parameter, as it quanties the semiconductor layer performance, specically with respect to current drive capability and maximum switching frequency. Two estimates for the carrier mobility are the incremental (inc ) and average (avg ) mobility. [148] While both estimates are assessed in the linear region of device operation (VDS 0 V), each has a unique physical interpretation. inc represents the mobility of incrementally induced carriers with changing gate voltage, assuming that carriers already present in the semiconductor have a constant mobility. avg represents the average mobility of all carriers in the semiconductor. For the 300 C processed device, inc and avg are 11 and 6 cm2 V1 s1 , respectively. For the 500 C processed device, inc and avg are 32 and 25 cm2 V1 s1 , respectively. The general shape of the mobility characteristic with respect to gate voltage, although not shown here, is very similar to previously reported zinc tin oxide TFTs. [160] Figure 4.5 shows the peak inc as a function of oxygen partial pressure in the sputtering ambient. The mobility increases to a peak at 0.8 mTorr, for both 300 C and 500 C semiconductor layer annealing. At higher oxygen partial pressures, mobility de-

71

35.0

m INC (cm2V-1s-1)

30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.5 0.6

500 C

300 C
0.7 0.8 0.9 1.0 1.1 1.2

O2 (mTorr)
Figure 4.5: Incremental mobility as a function of oxygen partial pressure for zinc tin oxide TFTs which are subjected to a 300 C and 500 C post-deposition anneal. creases. This is similar to reports for zinc oxide, tin oxide and tin-doped indium oxide. [150, 167, 168, 169] Turn-on voltage did not show a specic trend and is between -4 V and 2 V for all devices. A similar trend in mobility with respect to oxygen partial pressure is seen when the sputtering ambient is lowered to 5 mTorr total pressure. Mobility peaks at 0.8 mTorr of oxygen partial pressure and begins to decrease at oxygen partial pressures higher than 0.9 mTorr. Peak inc as high as 40 cm2 V1 s1 is achievable. However, the turn-on voltage is highly negative (less than -20 V) for all devices. This is indicative of oxygen vacancies in the zinc tin oxide which creates carriers and shifts the turn-on voltage negative.

72

10-2 10 10
-3 -4 -5 -6 -7 -8

500 C 300 C
o

ID (A)

10 10 10 10 10 10

10-9
-10 -11

-5

15

25

35

VGS (V)
Figure 4.6: Log(ID )VGS characteristics obtained at VDS = 40 V for two zinc tin oxide TFTs fabricated via reactive dc sputtering which are subjected to a 300 C and 500 C post-deposition anneal.

73 Figure 4.7 shows the DC bias of the target as a function of oxygen partial pressure at a constant sputtering pressure of 30 mTorr and constant power of 50 W. Notice that hysteresis is apparent between the forward sweep (increasing oxygen partial pressure) and backward sweep (decreasing oxygen partial pressure). This is common in reactively sputtered materials from a metal target. This hysteresis is indicative of target poisoning by the reactive gaseous species. In the case of zinc tin, on the forward sweep, the target surface is metallic up to 1 mTorr of oxygen partial pressure. On the reverse sweep the target surface is poisoned, i.e. covered with a thin zinc tin oxide layer, down to 0.5 mTorr of oxygen partial pressure. The region of optimal zinc tin oxide deposition is highlighted. This region is where the DC bias begins to decrease in magnitude with increasing oxygen partial pressure. This is also the optimal region for titanium nitride and titanium oxide deposition, where the deposition process retains the high deposition rate of a metal and the resultant lm is of the correct stoichiometry. [135, 170, 171] At lower oxygen partial pressures, the zinc tin oxide lm is anion decient, resulting in TFTs with large negative VON s. At higher oxygen partial pressures, the deposition rate decreases by an order of magnitude and the resultant TFTs exhibit very poor mobility values. In addition to a rf power source, sputtering using a dc power source is also explored. Figure 4.6 shows the log(ID )VGS characteristics (at VDS = 40 V) for two zinc tin oxide TFTs sputtered using a dc power source, with semiconductor layer anneals of 300 C and 500 C. The device exhibits fairly similar characteristics to the rf sputtered device. On-to-off ratio is > 107 for both devices, inverse subthreshold slope is 600 mV/decade

74

355

Negativ targ vo ve get oltage (-V) e

350 345 340 335 330 325 320 0 0.5 1

Region of optimal zinc tin oxide deposition

1.5

2.5

3.5

O2 Partial Pressure (mTorr)

Figure 4.7: DC bias on the target as a function of oxygen partial pressure at a constant sputtering pressure of 30 mTorr and constant power of 50 W. A forward sweep (increasing oxygen partial pressure), backward sweep (decreasing oxygen partial pressure), and the region of optimal zinc tin oxide deposition are shown.

75 and turn-on voltage is 0 V. Peak incremental mobiliites for the 300 C and 500 C processed devices are 8 cm2 V1 s1 and 31 cm2 V1 s1 , respectively. For these devices, the sputtering ambient and oxygen partial pressure are 30 mTorr and 0.9 mTorr, respectively. Similar to the rf sputtered devices, dc sputtered TFTs exhibit an optimal oxygen partial pressure, however in the dc case it is slightly higher, 0.9 mTorr. At higher and lower oxygen partial pressures peak inc decreases.

4.4

Conclusion
In this chapter, we demonstrate that zinc oxide-based TFTs with incremental mo-

bilities as high as 10 cm2 V1 s1 can be fabricated via reactive sputtering using a metallic target. In addition, devices fabricated near room temperature have incremental mobilities of 5 cm2 V1 s1 . Also, we demonstrate that zinc tin oxide-based TFTs with incremental mobilities as high as 32 cm2 V1 s1 can be fabricated via rf and dc reactive sputtering using a metallic target. Electrical characteristics of zinc oxide and zinc tin oxide lms deposited via reactive sputtering are shown to be strongly dependent on the oxygen ow rate during thin lm growth. The realization of oxide-based TFTs via reactive sputtering lends itself to commercial applications due to the higher obtainable deposition rates, and the cheaper, more durable nature of metallic targets; for zinc tin oxide, the price of the starting material is halved, while at comparable powers, the deposition rate is 4 as large.

76

5. THIN-FILM TRANSISTOR DIELECTRIC PERFORMANCE

5.1

Introduction
The purpose of this chapter is to examine several types of gate capacitance and

gate insulator trends in IGZO-based TFTs. Increasing the gate capacitance density is a straightforward way to improve the performance of a thin-lm transistor (TFT) since this leads to higher current drive at a given overvoltage, a decrease in the subthreshold swing, and a decrease in the magnitude of the turn-on voltage towards zero volts. This is demonstrated using various thicknesses of silicon dioxide deposited via chemical vapor deposition as the gate insulator in TFTs employing indium gallium zinc oxide (IGZO) as the semiconductor layer. The interface state density is estimated from a plot of the subthreshold swing versus the gate insulator thickness to be equal to 2 1012 cm2 and 1 1012 cm2 for TFTs in which the IGZO semiconductor layer is post-deposition annealed at 300 C and 500 C, respectively. Additionally it is shown that the choice of dielectric material greatly affects TFT performance. A comparison of chemical vapor deposited silicon dioxide, atomic layer deposited aluminum-titanium oxide, and chemical vapor deposited silicon nitride suggests that silicon dioxide is the best and silicon nitride is the worst choice of TFT gate insulator from the perspective of transfer curve hysteresis and turn-on voltage.

77

5.2

Experimental
Figure 5.1 shows a cross sectional view of a bottom-gate TFT. A silicon coupon

is used as the substrate with 1.75 m of PECVD silicon dioxide as an isolation layer. On top of the isolation layer, a gate electrode is formed consisting of titanium (10 nm,) aluminum:copper (100 nm,) titanium (10 nm,) and titanium nitride (40 nm.) The two layers of titanium are used as adhesion layers, while the aluminum:copper alloy is used as a high conductivity layer. The titanium nitride layer is used as a diffusion barrier to decrease the susceptibility of the gate electrode stack to thermal processing. A gate dielectric consisting of PECVD grown silicon dioxide from a silane (SiH4 ) source is deposited on top of the gate electrode stack. The silicon dioxide gate dielectric for this study is varied from 25 nm to 200 nm. TFTs utilizing aluminum titanium oxide(ATO) are fabricated on NEG OA2 glass coated with indium tin oxide for a bottom gate electrode and 220 nm of ATO. ATO is a proprietary, engineered insulator deposited by atomic layer deposition which consists of a thick cap of aluminum oxide, alternative thin layer of aluminum oxide and titanium oxide, and another thick cap of aluminum oxide. In this way, the high dielectric constant of the titanium oxide and the large bandgap (concomitant with low leakage current) of the aluminum oxide are combined to form a very low leakage insulator with a moderate dielectric constant (15). The gate capacitance density for the ATO is 60.3 nFcm2 . TFTs utilizing thermally grown silicon dioxide and silicon nitride are fabricated on moderately-doped (3 1016 cm3 ) silicon, which constitutes both the substrate and gate electrode. Thermally grown silicon dioxide is grown in a dry environment with a tantalum

78

Al

Al IGZO

SiO2 Ti/Al(Cu)/TiN/Ti SiO2 Silicon

Figure 5.1: Simplied cross-sectional view of the device structure used for this chapter. SiO2 is deposited via PECVD from a silane source, the gate electrode stack and IGZO are deposited via magnetron sputtering, and aluminum pads are deposited via thermal evaporation.

79 and gold back contact. Silicon nitride lms are grown via high density plasma chemical vapor deposition. The gate capacitance density for silicon dioxide and silicon nitride are 34.5 nFcm2 and 62.0 nFcm2 , respectively. An 40 nm indium gallium zinc oxide (IGZO) layer is then deposited via rf magnetron sputtering through a shadow mask for semiconductor denition using a 3 diameter ceramic sputter target purchased from Cerac, Inc. A target-to-substrate distance of 7.5 cm, a power of 100 W, and a pressure of 5 mTorr is used during the indium gallium zinc oxide deposition. After semiconductor deposition, an 100 nm layer of aluminum is deposited by thermal evaporation to form source/drain electrodes which are patterned through the use of shadow masks. The TFT device length and width are 200 m and 2000 m, respectively. Post-deposition annealing is accomplished in a Thermolyne 47900 box furnace. Samples are annealed at temperature for 1 hour.

5.3

Chemical Vapor Deposited (CVD) Silicon Dioxide

Log(ID )VGS transfer curves for IGZO-based TFTs fabricated using 100 nm of

thermally grown silicon dioxide and 100 nm of chemical vapor deposited silicon dioxide via a silane source are shown in Fig. 5.2. TFTs are annealed at 500 C. The inset shows ID VGS transfer curves for the same devices, however plotted on a linear scale. As seen from the gure, TFT current-voltage characteristics are almost identical for the two devices. Figure 5.3 shows the extracted incremental mobility for the devices of Fig. 5.2. Although the current-voltage characteristics for the TFTs exhibit very similar charac-

80

1.E-03

1.E-04 1.E-05 1.E-06

ID (A)

1.E-07 1.E-08 1.E-09 1.E-10 1.E-11

1.E-12 -10

10


30

50

Figure 5.2: Log(ID )-VGS transfer characteristics for IGZO-based TFTs utilizing thermally grown silicon dioxide and CVD grown silicon dioxide as the gate insulator. The IGZO semiconductor layer is post-deposition annealed in air at 500 C. (inset) ID -VGS transfer characteristics for the same devices, plotted on a linear scale. The TFTs are measured at VDS = 30 V.

81

25

(c 2V-1s-1) cm

20 15 10 5 0 0 10 20 30 40 50 60

inc

VGS - VON (V)

Figure 5.3: Extracted incremental mobility characteristics for IGZO-based TFTs utilizing thermally grown silicon dioxide and PECVD grown silicon dioxide as the gate insulator. The IGZO semiconductor layer is post-deposition annealed in air at 500 C. at 500 , as shown in Fig. 5.2. teristics, mobility extraction magnies any differences in device performance. One key point to note is that INC for the CVD TFT exhibits a peak value near VGS = 40 V. This peak and subsequent decline in incremental mobility is attributed to interface roughness scattering. [146] In contrast INC for the TFT with thermally grown silicon dioxide is still increasing in value at VGS = 60 V, indicating that a smoother surface is achieved with thermally grown silicon dioxide. Peak mobility for the two devices differ. However this difference is within the limits of experimental error, and could possibly be attributed to width-to-length variation during patterning of the source and drain electrodes.

82 Figure 5.4 shows the log(ID )-(VGS VON ) transfer characteristics for four IGZObased TFTs utilizing various thicknesses (25, 50, 100, and 200 nm) of CVD silicon dioxide from a silane source as the gate insulator. IGZO and aluminum pads are processed concurrently to reduce run-to-run variation. The overvoltage (VGS -VON ) is used in order to remove any variation due to the VON dependence with respect to the gate insulator. As seen from this gure, these devices perform in a relatively ideal manner, with the thinnest gate insulator (25 nm) corresponding to the highest gate capacitance density exhibiting the largest current drive and the TFT with the thickest silicon dioxide (200 nm), corresponding to the lowest gate capacitance density, exhibiting the lowest current drive. Additionally, the subthreshold swing decreases with reducing silicon dioxide thickness. Figure 5.5 shows the extracted incremental mobility as a function of gate-to-source voltage for IGZO-based TFTs utilizing various thicknesses of CVD silicon dioxide. There appears to be a trend with respect to peak mobility and gate dielectric thickness. However, these differences are within the limits of experimental error. The peak mobility occurs at 10, 20, 40, and 80 V for the 25, 50, 100, and 200 nm thick gate dielectric, respectively. The voltage at which the peak mobility occurs varies linearly with the gate dielectric thickness. This decrease in mobility with increasing VGS at larger values of VGS is again attributed to the interface roughness of the CVD silicon dioxide lm. The interface roughness begins to degrade mobility at an applied gate-to-source electric eld of 4.0 MVcm1 for all four TFTs. Figure 5.6 shows the turn-on voltage characteristics for the same devices as shown in Fig. 5.4. The turn-on voltage varies linearly with gate dielectric thickness, with a y-

83

1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07

Figure 5.4: Log(ID -VGS VON ) transfer characteristics for IGZO-based TFTs utilizing various thicknesses of silicon dioxide as the gate insulator. All TFTs are measured at VDS = 10 V.

1.00E-08 1.00E-09 1.00E-10 1.00E-11 0 2 4 6

25 nm 50 nm 100 nm 200 nm

10

84

20

50 nm 25 nm

100 nm

200 nm

cm2V-1s-1 m
INC

15

10

0 -5

15

35

55

75

VGS (V)

Figure 5.5: Extracted incremental mobility INC as a function of gate-to-source voltage for IGZO-based TFTs utilizing various thicknesses of CVD silicon dioxide as the gate insulator.

85 intercept of 0 V. The y-intercept at the origin indicates that the work function difference and oxide charge does not signicantly affect the turn-on voltage characteristics. By modeling the MOS gate structure as a simple capacitor, the free carrier concentration of a uniformly-doped depletion-mode TFT can be estimated by assuming that the turn-on voltage corresponds to the point where the semiconductor is fully depleted, i.e.

ND =

VON CI , q ts

(5.1)

where ND is the doping concentration, q is the fundamental electron charge, and ts is the thickness of the semiconductor (40 nm for these TFTs). From Fig. 5.6, ND is estimated to be 1 1017 cm3 . Figure 5.7 shows the subthreshold swing as a function of silicon dioxide gate dielectric thickness for TFTs fabricated at 300 and 500 C. The 500 C processed TFTs consistently exhibit lower subthreshold swing values. The subthreshold swing varies linearly with gate dielectric thickness, with both temperatures exhibiting a y-intercept of 60 mV decade1 . Additionally, the trend line for 200 C processed TFTs (not shown) intersects the y-axis near 60 mV/decade and results in DIT 2.1 1012 cm2 . The subthreshold swing (S) can be directly related to the interface trap density (DIT ) via [143] S= kT qDIT ln10 1 + q CI , (5.2)

where k is Boltzmanns constant (8.62 105 eVK1 ), T is the temperature in degrees Kelvin, q is the fundamental charge (1.60 1019 C), and CI is the capacitance density

86

Figure 5.6: Extracted turn-on-voltage VON as a function of CVD silicon dioxide thickness.









87

S Subth hreshold Swi d ing (m decad mV/d de)

SiO2 Thickness (nm)

Figure 5.7: Subthreshold swing as a function of CVD silicon dioxide thicknesss for IGZO-based TFTs annealed at 300 C and 500 C The interface state density for each annealing temperature is also indicated..

300 C
DIT = 2e12 cm-2eV-1

500 C
DIT = 1e12 cm-2eV-1

88 of the gate insulator. Substituting CI = I , tI (5.3)

where I is the dielectric constant of the insulator and tI is the thickness of the insulator, into Eq. 5.2 yields S= kT qDIT tI ln10 1 + q I , (5.4)

Note that the subthreshold swing is directly proportional to the insulator thickness. Thus a plot of S versus tI , such as given in Fig. 5.7, possesses a slope of y-intercept of
kT q ln10. qDIT kT q ln10 I

and a

Thus, DIT may be found directly from the slope of a S versus tI

plot. The interface of IGZO and PECVD silicon dioxide exhibits an interface trap density of DIT = 2 1012 cm2 eV1 after a 300 C post-deposition anneal. At a higher anneal temperature of 500 C, the interface trap density is reduced to 1 1012 cm2 eV1 . Additionally, the trend line for a 200 C anneal (not shown) intersects the y-axis near 60 mV/decade and results in DIT 2.1 1012 cm2 . In contrast, polycrystalline silicon on silicon dioxide processed at a temperature of 600 C exhibits a trap density of 1 1011 cm2 eV1 [172], single crystal silicon with thermally-grown silicon dioxide exhibits a trap density of 3 1010 cm2 eV1 [173], and an organic TFT device utilizing optimized single crystal rubrene on silicon dioxide, 2 1012 cm2 eV1 [174].

5.4

Silicon Dioxide, Aluminum Oxide, and Silicon Nitride

Figure 5.8 shows the log(ID )-VGS transfer characteristics for two separate IGZO-

based TFTs utilizing thermally grown silicon dioxide as the gate dielectric and annealed

89

VGS (V)

Figure 5.8: Log(ID )-VGS transfer characteristics for IGZO-based TFTs utilizing thermally grown silicon dioxide as the gate insulator. The TFT is measured at VDS = 1 V.

  

500 C

300 C

90

VGS (V)

Figure 5.9: Log(ID )-VGS transfer characteristics for IGZO-based TFTs utilizing CVD silicon dioxide as the gate insulator. The TFT is measured at VDS = 1 V. at 300 and 500 C. As the temperature increases, the turn-on voltage for the device is shifted more negative, due to reduction in trap density. Additionally, a small amount of clockwise hysteresis is present in the TFT that is processed at 300 C, which is not seen in the TFT that is processed at 500 C. This decrease in hysteresis is attributed to a reduction in the density of interfacial defects by the high temperature anneal. Extracted incremental mobilities are 20 cm2 V1 s1 for both the 300 C and 500 C processed TFTs. Figure 5.9 shows the log(ID )-VGS transfer characteristics for two separate IGZObased TFTs utilizing CVD silicon dioxide as the gate dielectric and annealed at 300 and

  

500 C

300 C

91

VGS (V)

Figure 5.10: Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing ALD deposited aluminum oxide:titanium oxide as the gate insulator. The TFT is measured at VDS = 1 V. 500 C. The characteristics are nearly identical to those of the thermally grown silicon dioxide. As the temperature increases, the turn-on voltage for the device is shifted more negative, due to a reduction in trap density. Additionally, a small amount of clockwise hysteresis is present in the TFT that is processed at 300 C, which is not seen in the TFT that is processed at 500 C. This decrease in hysteresis is attributed to a reduction in the density of interfacial defects by the high temperature anneal. Extracted incremental mobilities are 19 cm2 V1 s1 for both the 300 C and 500 C processed TFTs.

  

500 C

300 C

92 Figure 5.10 shows the log(ID )-VGS transfer characteristics for two separate IGZObased TFTs utilizing ALD grown aluminum oxide:titanium oxide (ATO) as the gate dielectric and annealed at 300 and 500 C. Similar to the silicon dioxide devices, as the temperature increases, the turn-on voltage for the TFTs is shifted more negative, due to reduction in trap density. ATO TFTs exhibit a more positive VON at 300 C, when compared to their silicon dioxide counterparts, indicative of a higher empty trap concentration. At a processing temperature of 500 C, the ALD ATO and thermally grown silicon dioxide exhibit similar VON s. A dramatic clockwise hysteresis is present in the TFT that is processed at 300 C, which is not seen in the TFT that is processed at 500
C.

This is attributed, once again, to a reduction in the density of interfacial defects by

the high temperature anneal. Extracted incremental mobilities are 8 cm2 V1 s1 and 10 cm2 V1 s1 for the 300 C and 500 C processed TFTs, respectively. A high temperature post-deposition anneal can improve TFT characteristics via three methods: improvement of the semiconductor layer, improvement of the dielectric layer or improvement of the semiconductor-dielectric interface. If the improvements to TFT characteristics are due to improvements to the semiconductor layer, TFT characteristics would be the same regardless of the dielectric used. Due to the fact that TFTs utilizing silicon dioxide as the dielectric and annealed at 300 do not show the same characteristics as those utilizing ATO, the improvement to the semiconductor layer is unlikely. To analyze the possibility of improvement of the dielectric layer, a high temperature anneal is performed to the gate dielectric prior to the semiconductor deposition. Figure 5.11 shows the log(ID )-VGS transfer characteristic for a TFT where the ATO dielectric is an-

93

VGS (V)

Figure 5.11: Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing ALD deposited aluminum oxide:titanium oxide as the gate insulator. For this TFT, the aluminum oxide:titanium oxide is annealed to 500 C prior to the semiconductor deposition, and the TFT stack is annealed at 300 C after the semiconductor deposition. The TFT is measured at VDS = 1 V.

  

94 nealed at 500 C prior to the IGZO deposition. After the IGZO deposition, the TFT stack is annealed at 300 C. The characteristics for this device are nearly identical to that of the 300 C annealed device shown in Fig. 5.10. The similarity in log(ID )-VGS transfer characteristics indicates that improvements to the dielectric is unlikely the cause of the poor TFT characteristics when annealed at 300 C. Thus, the improvement in TFT characteristics after a 500 anneal for TFTs utilizing ATO as the gate dielectric is attributed to improvements to the semiconductor-dielectric interface. Hysteresis in TFTs utilizing aluminum oxide as the gate dielectric is seen in other studies as well. Electron beam evaporated aluminum oxide with zinc oxide processed at temperatures up to 200 C as a semiconductor layer also exhibited signicant hysteresis, although zinc oxide on ALD aluminum oxide exhibited minimal hysteresis. [98] Carcia et al attribute hysteresis, or the lack thereof, to the quality of the interface between the zinc oxide and aluminum oxide. Additionally, for the same processing parameters TFT mobility varied drastically, depending on which gate dielectric is utilized, varying from 0.3 cm2 V1 s1 on thermally grown silicon dioxide to 17.6 cm2 V1 s1 on ALD aluminum oxide. The higher mobility seen in aluminum-oxide-based TFTs is contrary to the trends presented in this chapter. The contrasting data is a result of two different approaches. Carcia et al optimized their zinc oxide process for deposition on aluminum oxide. Subsequently, they used the same processing conditions to fabricate zinc oxide devices on silicon dioxide. For the data shown in this chapter, IGZO deposition parameters are optimized for processing on silicon dioxide, and subsequently the same processing parameters are utilized for aluminum oxide and silicon nitride devices. This indicates that

95

VGS (V)

Figure 5.12: Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing CVD deposited silicon nitride as the gate insulator. The TFT is measured at VDS = 1 V. with improved process optimization, stable IGZO-based TFTs with an ALD aluminum oxide gate dielectric are feasible at lower processing temperatures. Figure 5.12 shows the log(ID )-VGS transfer characteristics for two separate IGZObased TFTs utilizing CVD silicon nitride as the gate dielectric and annealed at 300 and 500 C. Extracted incremental mobilities are 8 cm2 V1 s1 and 11 cm2 V1 s1 for the 300 C and 500 C processed TFTs, respectively. The turn-on voltage and clockwise hysteresis present in the IGZO TFT annealed at 300 C given in Fig. 5.12 is similar to that shown in Fig. 5.10 when atomic layer deposited aluminum-titanium oxide is used

  

300 C 500 C

96 as the gate insulator. However, when silicon nitride is used as the gate insulator, the 500 C anneal shifts the turn-on voltage in a positive direction and increases the amount of hysteresis present in the transfer curve. This 500 C compared to 300 C annealing trend is opposite of that found for thermal silicon dioxide, as shown in Fig. 5.8, and for atomic layer deposited aluminum-titanium oxide, as indicated in Fig. 5.10. These turnon voltage and transfer curve hysteresis trends suggest that silicon nitride is a poor gate insulator choice for IGZO TFTs. Note that oxygen is a common anion for silicon dioxide and aluminum-titanium oxide gate insulators in conjunction with IGZO, while silicon nitride and IGZO have different anions. A possible instability mechanism involves the presence of hydrogen in the silicon nitride lm, resulting in a high trap density at the silicon nitride IGZO interface. Another possible mechanism is the anion exchange of nitrogen and oxygen, which may account for the anomalous turn-on voltage and transfer curve hysteresis trends found in silicon nitride-IGZO TFTs. Regardless of the actual atomic instability mechanism, these turn-on voltage and transfer curve hysteresis trends suggest that silicon nitride is a poor gate insulator choice for IGZO TFTs. Souza et al reports that zinc oxide deposited via PLD for zinc oxide-based TFTs on silicon nitride exhibits signicant hystersis. [175] However, Carcia et al and Cross et al report minimal hysteresis with respect to zinc oxide-based TFTs utilizing silicon nitride as the gate dielectric with minimal hysteresis. [176, 20] In these two cases, all processing is carried out at or below 150 C. This indicates that high processing temperatures (> 300 C) create defects at the silicon nitride-IGZO interface, resulting in a positive turn-on voltage and signicant hysteresis.

97

VGS (V)

Figure 5.13: Log(ID )-VGS ) transfer characteristics for IGZO-based TFTs utilizing thermal silicon dioxide, CVD deposited silicon dioxide from a silane (SiH4 ) precursor and CVD via a TEOS (SiC8 H20 O4 ) precursor. The TFTs are measured at VDS = 1 V.

 

Thermally grown

TEOS precursor SiH4 precursor

98

5.5

Silane and Tetraethyl Orthosilicate (TEOS)-based CVD

With respect to silicon dioxide as a gate dielectric, three sources are compared,

thermally grown silicon dioxide via dry oxidation, CVD silicon dioxide from a TEOS source, and CVD silicon dioxide from a silane source. The IGZO layer is processed at 300 C for these TFTs. All three samples are grown utilizing silicon as the substrate and the IGZO semiconductor layers are processed concurrently. The turn-on voltage for the devices did not vary signicantly, 2 V, 1.5 V, and 2.8 V for the thermal, TEOS, and silane silicon dioxide, respectively. The subthreshold swing did exhibit variation, S = of 337, 466, 570 mV/decade for the thermal, TEOS, and silane-based silicon dioxide. The subthreshold slope variation is attributed to hydrogen and hydroxide in the dielectric lm, resulting in an increased interface trap density. No hydrogen or hydroxide groups are present during the formation of the dry thermally grown silicon dioxide, which represents the lowest subthreshold slope and thus the lowest interface trap density. In the case of TEOS- and silane-based silicon dioxide, both depositions involve the use of hydroxide groups. However the formation of a dense, lower defect density silicon dioxide from TEOS is due to its lower activation energy. [177] TEOS-based silicon dioxide performs better for polysilicon-based TFTs as well. [178] In the case of TEOS- and silane-based silicon dioxide on polycrystalline silicon, the interface trap density is found to be 1 1011 cm2 eV1 and 1.5 1011 cm2 eV1 , respectively.

99

5.6

Conclusion
In this chapter it is demonstrated that chemical vapor deposited silicon dioxide at

low applied elds behaves in a nearly identical fashion to thermally grown silicon dioxide when utilized as a dielectric layer in thin-lm transistors annealed at 500 C. At high applied elds, the interfacial roughness of the chemical vapor deposited silicon dioxide detrimentally affects TFT performance. Additionally, increasing the gate capacitance density is demonstrated to improve the performance of an IGZO TFT, yielding a higher current drive, a decrease in the subthreshold swing and a decrease in the magnitude of the turn-on voltage. The interface state density for IGZO on CVD silicon dioxide is estimated to be 2.1 1012 cm2 eV1 , 2 1012 cm2 eV1 , and 1 1012 cm2 eV1 for TFTs annealed at 200 C, 300 C, and 500 C, respectively, in conjunction with chemical vapor deposited silicon dioxide as the gate insulator. Finally, silicon nitride appears to be a poor gate insulator choice for IGZO TFTs, based on turn-on voltage and transfer curve hysteresis trends, with silicon dioxide via a TEOS source exhibiting the best TFT characteristics of the CVD precursors investigated.

100

6. OXIDE SEMICONDUCTOR THIN-FILM TRANSISTOR TWO-TERMINAL ASSESSMENT

6.1 Introduction
Several recent studies have reported on the trap properties of oxide semiconductors using optical [179, 180] or capacitance measurements [181]. Although these methods are useful for trap assessment, both optical and capacitance methods require fabrication of specialized device structures. Additionally, optical characterization provides an estimate of a convolution of states above the valence band maximum and below the conduction band minimum, rather than a direct picture of trap states near the conduction band minimum, which is of primary interest with regard to thin-lm transistor (TFT) operation. By analyzing the two-terminal current-voltage characteristics of indium gallium zinc oxide (IGZO) TFTs, information related to trap states within the IGZO semiconductor can be obtained. This method provides a very simple path to trap assessment. Extracted trap properties, particularly the trap energy, ET , correlate quite well with IGZO TFT performance.

6.2

Experimental
Figure 6.1 shows a cross section of the device structure used in this chapter. TFTs

are fabricated on moderately-doped (3 1016 cm3 ) silicon, which constitutes both the substrate and gate electrode. Thermal silicon dioxide is grown in a dry environment with

101 a tantalum and gold back contact. The gate capacitance density for this 100 nm thick silicon dioxide is 34.5 nFcm2 . An 70 nm IGZO layer is then deposited via rf magnetron sputtering through a shadow mask for semiconductor denition using a 3 diameter ceramic sputter target purchased from Cerac, Inc. A target-to-substrate distance of 7.5 cm, a power of 100 W, and a pressure of 5 mTorr is used during the IGZO deposition. Oxygen partial pressure during the IGZO deposition is 7.4 Torr, with the remainder of the sputtering ambient composed of argon. Post-deposition annealing is accomplished in a Thermolyne 47900 box furnace. Samples are annealed at temperature for 1 hour. After semiconductor deposition and annealing, an 200 nm layer of aluminum is deposited by thermal evaporation to form source/drain electrodes which are patterned through the use of shadow masks. The TFT device length and width are 200 m and 2000 m, respectively. The aluminumIGZO overlap is 200 m 2000 m.

6.3

Transistor characteristics
Figure 6.2 shows the current-voltage characteristics for an IGZO TFT with a post-

deposition anneal of 300 C. The main gure represents the log(ID )-VGS transfer characteristics for the device with VDS = 30 V. The turn-on voltage for this device is 3 V and the drain current on-to-off ratio is > 106 . The inset shows the ID -VDS output characteristics for the device operated at VGS = 0, 10, 20, and 30 V. This TFT exhibits qualitatively ideal characteristics, including hard drain current saturation.

102

200 Al (200 nm)

IGZO (70 nm) Silicon dioxide (100 nm)

Silicon (p+)

Figure 6.1: Cross sectional view of the test structure used for this chapter. The silicon and silicon dioxide constitute the gate electrode and gate dielectric, respectively. The aluminum pads are the source/drain contacts and indium gallium zinc oxide (IGZO) constitutes the semiconductor layer.

Al (200 nm)

103

1.E-03 1.E-04

C ent A) Curre (A

1.E-05 1.E-06

ID
ID (mA)

0.45 0.4 0.35 0 35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 10 20 30

1.E-07 1 E-07 1.E-08 1.E-09 1.E-10 1.E-11 0.0 10.0

VDS (V)

IG
20.0 30.0 40.0

VGS (V)

Figure 6.2: Log(ID )-VGS transfer characteristics obtained at VDS = 30 V for an IGZO TFT post-deposition annealed at 300 C. (inset) Drain current-drain voltage (ID -VDS ) output characteristics for the same device. VGS is decreased from 30 V (top curve, showing maximum current) to 0 V in 10 V steps. Note that the VGS = 10 V and 0 V curves overlap with the x-axis.

104

6.E-08 6 E 08 5.E 08 5 E-08 4.E-08 Floating Gate (M-S-M operation)

ID (A)

3.E-08 2.E-08 1.E-08

VGS = 0 V 0.E+00 0 10 20 30

VDS (V)

Figure 6.3: Current-voltage characteristics for an IGZO TFT operated as a two-terminal M-S-M (Al-IGZO-Al) device. Voltage is applied to the drain with the source grounded for two situations: with the gate electrode oating and with VGS = 0 V. The IGZO TFT employed is subjected to a 300 C post-deposition anneal.

6.4

Metal-Semiconductor-Metal Current-Voltage Characteristics

Figure 6.3 shows ID -VDS characteristics for an IGZO-based TFT post-deposition

annealed at 300 C. Two curves are shown, VGS = 0 V and with a oating gate electrode. Note that ID is negligible when VGS = 0 V, consistent with the positive turn-on voltage of Fig 6.2. In contrast, with the gate electrode oating, ID exhibits a superlinear relationship with applied voltage. Figure 6.4 shows two-terminal metal-semiconductor-metal (M-S-M) current-voltage characteristics obtained with a oating gate and plotted on a log-log scale for IGZO TFTs post-deposition annealed at 300, 400, 500, and 600 C. For these devices, two regions

105 of conduction are visible. In the low voltage regions, the slope of the log-log plot is 1 decade/decade, indicative of ohmic conduction. In this region the free carrier concentration (n0 ) can be obtained from Ohms law by using [182]

V I = Wts qn0 , L

(6.1)

where W and ts are the width and thickness of the semiconductor region, q is the fundamental charge of an electon, V is the applied voltage, and L is the distance from the source contact to the drain contact. Extracted n0 values are shown in Table 6.1. At higher applied voltages, the slope of the log-log plot increases to a value > 2, indicating that the dominant conduction mechanism in this region is space-charge-limited current. For an amorphous semiconductor, such as IGZO, an exponential band tail density of states is expected,

Nt (E) =

EEC Nt EEC e kB Tt = N0 e kB Tt , kB Tt

(6.2)

where Nt (E) is the concentration of traps per unit energy (cm3 eV1 ) centered at an energy E, Nt is the total trap density (cm3 ), N0 is the concentration of traps per unit energy (cm3 eV1 ) evaluated at the conduction band minimum energy, EC , Tt is a temperature parameter characterizing the trap distribution, and kB is Boltzmanns constant. These band tail states function as trap states. [3, 180, 181] Bulk space-charge-limited current

106

1.E-03 1.E 04 1 E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1 E 11 1.E-12 1.E-13 3 1.E-14

Increasing anneal temperature

Curre (A ent A)

1.E-02

1.E-01

1.E+00

1.E+01

Applied Voltage (V)

Figure 6.4: Current-voltage characteristics of four IGZO TFTs operated as two-terminal M-S-M (Al-IGZO-Al). Voltage is applied to the drain with the source grounded and the gate electrode oating. Four different post-deposition anneal temperatures (300(diamond), 400(square), 500(triangle), 600(X) C) are shown.

107 through a material with an exponential trap distribution is characterized by [182]

m m+1

I = Wts NC q1m

m Nt (m + 1)

2m + 1 m+1

V m+1 , L2m+1

(6.3)

where W and ts are the width and thickness of the semiconductor, q is the fundamental charge of an electon, NC is the effective density of states in the conduction band, is the bulk carrier mobility, is the dielectric permittivity of the semiconductor, V is the applied voltage, and L is the device length. The variable m is dened as

m=

Tt , T

(6.4)

where T is the measurement temperature and Tt is a temperature parameter characterizing the trap distribution which can be related to the characteristic trap energy (ET ) via Boltzmanns constant (kB ), i.e. ET = kB Tt . (6.5)

To accomplish trap parameter extraction, is it convenient to take the logarithm of both sides of Eq. 6.3, yielding
m m+1

log(I) = log Wts NC q1m

m Nt (m + 1)

2m + 1 m+1

1 L2m+1

+ (m + 1)log(V ). (6.6)

Note that this equation has the form of a linear equation. Estimation of m is accomplished by recognizing that the slope of the line is (m+1). The rst term on the right side of Eq.

108 6.6 corresponds to the y-intercept of the linear equation. With m known from assessment of the slope, all of the other y-intercept parameters, i.e. W, Ts , L, NC , , and m, are known except for Nt and possibly . Thus Nt can be estimated from an evaluation of the y-intercept. The accuracy to which Nt may be assessed depends on the accuracy to which is known and also on the y-intercept uncertainty. Most of the Nt variability associated with estimation of the y-intercept since it is located relatively remotely from the data points from which it is predicted. In contrast, the accuracy of Nt does not depend critically on the assumed value of . For example, the rst entry for Nt of Table 6.1 changes from 9 1014 cm3 to 9.8 1014 cm3 when the mobility is assumed to be 40 cm2 V1 s1 rather than the value of 20 cm2 V1 s1 used in the actual assessment. Additionally, from the extrapolated value of m and using Eq. 6.4, a value for Tt can be calculated, and subsequently from Eq. 6.5 a value for ET .

Table 6.1: A summary of IGZO TFT properties for various post-deposition anneal temperatures. Incremental mobility INC and turn-on voltage (VON ) are obtained from three-terminal TFT assessment while space-charge-limited parameters, i.e., characteristic trap energy and temperature, ET and Tt , total trap density, Nt , trap concentration per unit energy evaluated at the conduction band minimum, N0 , are obtained from two-terminal measurements between the source and drain with the gate oating. The following values are used in the estimation of Nt and N0 : NC = 5.0 1018 cm3 , = 20 cm2 V1 s1 , and S = 1.0 1010 Fcm1 . INC (cm2 V1 s1 ) 13.6 14.9 18.6 18.9 VON (V) 4 2 0 0 ET (meV) 130 80 60 50 Tt (K) 1530 913 687 554 Nt (cm3 ) 9 1014 2 1015 8 1014 1 1015

Anneal ( C) 300 400 500 600

N0 (cm3 eV1 )
6 1015 3 1016 1 1016 3 1016

n0 (cm3 ) unmeasurable unmeasurable 6 1012 2 1013

109

110

1.E+17 1 E+17 1.E+16 1 E 16

Nt (c -3eV-1) cm V

1.E+15 1.E+14 1.E+13 1.E+12 0 0.1 0.2 0.3 0.4 0.5

Increasing anneal temperature

EC-E (eV)

Figure 6.5: Estimated band tail state density distribution (Nt (E)) near the conduction band minimum for IGZO annealed at 300, 400, 500, 600 C. Table 6.1 compiles extracted IGZO TFT and space-charge-limited current parameters. Note that there is a strong correlation between mobility and characteristic trap energy with respect to the post-deposition anneal temperature. Specically, with increasing anneal temperature, mobility increases while the characteristic trap energy decreases. VON also decreases while n0 increases with increasing post-deposition annealing temperature. Finally, Nt and N0 appear to be almost constant and display no obvious trend with respect to post-deposition annealing temperature. Figure 6.5 shows estimated band tail state density (Nt (E)) distributions corresponding to the N0 and ET values compiled in Table 6.1 for IGZO annealed at 300, 400, 500, 600 C. Although the total number of traps (Nt ), as tabulated in Table 6.1, does not vary

111 signicantly for the different anneal temperatures, the band tail state distribution is greatly affected by the anneal temperature. As the post-deposition anneal temperature increases, the band tail state distribution is spread across a smaller fraction of the bandgap. Conversely as the post-deposition anneal temperature decreases the estimated band tail state distribution widens. This post-deposition annealing trend is easier to see if it is assumed that N0 is a constant, allowing Fig 6.5 to be replotted as shown in Fig 6.6. This gure clearly indicates that band tail state density spreads out over a smaller range of energy with increasing post-deposition annealing temperature. This means that for a higher postdeposition annealing temperature fewer band tail states need to be lled with electrons as the Fermi level approaches EC . In turn, when the Fermi level is able to more closely approach EC , more extended conduction band states may be populated, leading to an improved mobility with increasing post-deposition annealing temperature. It is difcult to directly compare the band tail state density distribution obtained herein for IGZO to those previously reported in the literature. Hsieh et al. employ a device simulator to estimate the band tail state distribution of IGZO TFTs prepared by pulsed laser deposition and post-deposition annealing at 300 C. For enhancement-mode devices, such as fabricated herein, they report N0 = 5 1016 cm3 eV1 and ET = 1.0 eV for a model, model 1, involving band states only, and N0 = 2.3 1018 cm3 eV1 and ET = 80 meV for a model, model 2, involving both band tail and deep gap states. Their model 1 value for N0 is approximately one order of magnitude greater than our 300 C estimate, while their model 2 estimate is almost two orders of magnitude greater. Some of

112

1.E+17 1 E+17 1 E 16 1.E+16

Nt (c -3eV-1) cm V

1.E+15 1.E+14 1.E+13 1.E+12 0 0.1 0.2 0.3 0.4 0.5

Increasing anneal temperature

EC-E (eV)

Figure 6.6: Estimated band tail state density distribution (Nt (E)) near the conduction band minimum for IGZO annealed at 300, 400, 500, 600 C assuming a constant value of N0 for all annealing temperatures. this difference can be attributed to the fact that their extraction procedure is based on the assessment of accumulation layer electrons which are in very close physical proximity to the insulator-semiconductor interface while space-charge-limited current presumably involves electrons transiting within the IGZO bulk. Interface trap densities are expected to be larger than that of the bulk. Note that Hsieh et al. prefer their model 2 t to their data. The model 2 trap energy of 80 meV is closer to the 130 meV value herein found for the IGZO sample annealed at 300 C.

113

6.5

Conclusion
In this chapter a simple method to characterize the band tail state distribution near

the conduction band minimum of a semiconductor by analyzing two-terminal currentvoltage characteristics of a TFT with a oating gate is presented. The characteristics trap energy (ET ) as a function of post-deposition annealing temperature is shown to correlate very well with IGZO TFT performance, with a lower value of ET , corresponding to a more abrupt distribution of band tail states, correlating with improved TFT mobility.

114

7. CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK

The focus of this research is towards the commercialization of oxide-based thin-lm transistors. As such, there are two primary focuses for this dissertation, the utilization of a commercially feasible route (reactive sputtering from a metal target) towards fabrication of oxide-based thin-lm transistors (TFTs) and an exploration of the effect of gate dielectric variations on TFT device performance. Reactive sputtering using a metallic target has several advantages compared to deposition methods in which a ceramic target is used. [135, 150] Reactive sputtering using a metallic target usually results in a higher deposition rate. The physical properties of the metal lead to a more durable target of higher purity and superior thermal conductivity. Finally, a metallic target is easier to fabricate, requiring less care and cost than is involved in the fabrication of a ceramic target. By utilizing sputtering from a metal target TFT performance on par or better than those from a ceramic target is achievable. By varying oxygen partial pressure, optimized zinc oxide TFTs with mobilities of 10 cm2 V1 s1 can be fabricated via reactive sputtering using a metallic target. In addition, devices fabricated near room temperature have incremental mobilities of 5 cm2 V1 s1 . Also, it is demonstrated that zinc tin oxide-based TFTs with incremental mobilities as high as 32 cm2 V1 s1 can be fabricated via rf and dc reactive sputtering using a metallic target. By utilization of a metal target, a cheaper and faster route towards oxide semiconductor deposition is achieved.

115 TFT characteristics are shown to be dominated by the semiconductor-dielectric interface, with silicon dioxide via a TEOS source material being shown to be a relatively optimal candidate as a gate dielectric for TFT performance. Additionally for each dielectric material, it is hypothesized that deposition parameters for the semiconductor have to be optimized specically for each dielectric material. It is demonstrated that chemical vapor deposited silicon dioxide at low applied elds behaves identically to thermally grown silicon dioxide when utilized as a dielectric layer in thin-lm transistors annealed at 500 C. At high applied elds, the interfacial roughness of the chemical vapor deposited silicon dioxide detrimentally affects TFT performance of the insulators investigated. Increasing the gate capacitance density is demonstrated to improve the performance of an IGZO TFT, yielding a higher current drive, a decrease in subthreshold swing, and a decrease in the magnitude of the turn-on voltage. The interface state density for IGZO on CVD silicon dioxide is estimated to be 2.1 1012 cm2 eV1 , 2 1012 cm2 eV1 , and 1 1012 cm2 eV1 for TFTs annealed at 200 C, 300 C, and 500 C, respectively, in conjunction with chemical vapor deposited silicon dioxide as the gate insulator. Additionally, silicon nitride appears to be a poor gate insulator choice for IGZO TFTs, based on turn-on voltage and transfer curve hysteresis trends, with silicon dioxide via a TEOS source exhibiting the best TFT characteristics. Finally, a simple method to characterize the band tail state distribution near the conduction band minimum of a semiconductor by analyzing two-terminal current-voltage characteristics of a TFT with a oating gate is presented. The characteristics trap energy

116 (ET ) as a function of post-deposition annealing temperature is shown to correlate very well with IGZO TFT performance, with a lower value of ET , corresponding to a more abrupt distribution of band tail states, correlating with improved TFT mobility.

7.0.1 Recommendations for future work

1. Dielectric-semiconductor interface: The majority of carrier movement in TFTs occurs at the semiconductor-dielectric interface. It follows that the semiconductordielectric interface is crucial to proper TFT operation, as shown in this thesis. Further studies into techniques such as a low energy in-situ plasma clean prior to the semiconductor deposition or sequential deposition of the dielectric and semiconductor layers while maintaining high vacuum may yield TFTs with improved performance. 2. Circuit integration: IGO and IGZO-based ring oscillators have been reported, but it may be useful to attempt other circuits, such as current mirrors or logic gates. These circuits place additional requirements on the TFT, such as congruency (for the current mirror), and may be useful in learning the limits of this nascent technology. 3. Vertical integration: Up to this point circuit layout utilizing thin-lm transistor has consumed horizontal surface coverage. Additionally, the effect of stacking TFTs vertically on device performance is an interesting venue. This approach can increase display performance two fold: increased switching speed due to higher current drive and higher resolution due to smaller pixel size. Additionally, with

117 respect to circuit performance, the parasitic resistance can be reduced by reducing interconnect distances between TFTs. 4. Device stability: It is important to investigate the physical mechanisms (such as hydrogen diffusion in a-Si:H TFTs) that hinder device stability. Testing of devices at different temperatures may also be useful; this testing methodology can be used to extract an activation energy related to device degradation and can be helpful in tting oxide semiconductor-based TFT stability data to a degradation model. Additionally the testing of various device structures, such as passivated TFTs or dual-gate TFTs, can aid in the analysis of instability and recovery mechanisms. 5. Alternative processing: In this study, temperatures up to 500 C are utilized to improve device performance. This is appropriate when glass is the intended substrate, however to move from transparent electronics towards exible electronics requires the reduction of processing temperatures. Alternatives to thermal processing, such as laser annealing, microwave treatment, or localized heating via electrical conduction should be studied as a route towards lower temperature processing. 6. Frequency analysis: Several ring oscillators have been fabricated utilizing oxidebased TFTs, however the performance of these circuits, operating at frequencies less than 5 MHz, has been limited by interconnect resistance and parasitic capacitance. How these oxide semiconductors operate at higher frequencies and whether there is an inherent limitation to their high frequency operation will eventually limit the utilization of oxide based TFTs.

118 7. Semiconductor layer structure: To date, most TFTs utilize a homogenous semiconductor layer. The one exception is the initial IGZO report by Nomura et al. [129] where the single crystal semiconductor layer consisted of two individual components, an InO layer, parallel to the dielectric-semiconductor interface, which al2 lowed electron conduction and a GaO(ZnO5 )+ layer which controlled carrier doping. A similar structure composed of amorphous materials, with a carrier transport layer capped with a layer to limit carrier doping might be utilized to form a TFT with a high mobility and turn-on voltage near 0 V. 8. Exploration of degenerate oxide semiconductors: In addition to semiconductor layer exploration, alternative degenerate oxide semiconductors should be investigated due to the limited supply of In and as a means to reduce parasitic resistance that degrades circuit performance. A degenerate p-type semiconductor might be the key to realization of an oxide-based p-type TFT. 9. Exploration of p-channel TFTs: Exploration of p-channel TFTs is recommended as a means of realizing a complementary circuit technology with oxide-based TFTs. Potential semiconductor materials include NiO and Cu2 O. Additionally, note that hole injection will likely pose a difcult challenge in forming these TFTs. One drawback is that most p-type oxides either have poor mobility or require a high temperature annealing treatment to achieve reasonable performance.

119

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