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Table Of Contents

1 INTRODUCTION
1.1 Brief Overview of Microprocessor Evolution
Figure 1-1. Exponential increase of transistors per die
Figure 1-2. Current and voltage roadmap for present and future microprocessors
1.2 Microprocessor Power Delivery and Load Characteristics
Figure 1-3. Voltage regulator providing power to the microprocessor
Figure 1-5. Voltage regulator module, VRM
1.3 The Role and Operation of a Voltage Regulator
1.4 Off-Chip VR Alernatives
Figure 1-7. Laptop power supply
Figure 1-12. On-chip voltage regulator module [1]
1.6 Thesis Outline
2 VOLTAGE REGULATOR TOPOLOGIES
Figure 2-1. Power distribution noise in a system on a chip [5]
2.1 Complete Survey of all On-Chip VRM Topologies
2.1.1 Linear Regulators
2.1.2 Switching Regulators
Figure 2-3. Switching regulator
2.2 Other On-Chip-Friendly VR Topologies
2.2.1 Switched Capacitor Circuits (Charge Pumps)
Figure 2-4. Switched capacitor regulator [14]
2.2.2 MEMS Approach (DC/DC Converters with MEMS Inductors)
2.2.3 Inductor Multiplier Technique
Figure 2-5. Switching regulator employing inductor multiplier [14]
2.3 Relative Merits/Demerits of Each Option
2.4 On-Chip VRM Issues
3 ON-CHIP VRM FOR SINGLE AND DUAL CORE SYSTEMS
Figure 3-1. Intel dual core processor, from Intel website
3.1 Single-Core Voltage Regulation
3.2 Buck-Type Switching Regulator for On-Chip Implementation
Figure 3-2. Switching Regulator with hysteresis control
Figure 3-3. Inductor Current in Switching Converter
3.3 Implementation Challenges
3.4 Hot Swap Controller Solution
Figure 3-4. Regulator off-chip a) without controller and b) with controller
Figure 3-5. Regulator and controller on-chip
4.1 Hybrid Two-Stage Regulator
4.2 Stage 1: Switching Regulator
Figure 4-3. Switching regulator
Figure 4-4. Switching regulator with switch ON
Figure 4-5. Switching regulator with switch OFF
Figure 4-6. PWM, duty cycle of the switching regulator
Figure 4-8. Waveform of current through PMOS transistor
Figure 4-10. Current through inductor/output current
Table 1. Switching Regulator Circuit Parameters
4.2.1 Pulse Width Modulation (PWM)
4.2.2 Switching Regulator Efficiency
Figure 4-12. Switching regulator efficiency
4.3 Stage-2: Low Dropout Linear Regulator (LDO)
Figure 4-13. Linear dropout regulator
4.3.1 Pass Element
4.3.2 Error Amplifier
Figure 4-15. Class-A amplifier
4.3.3 Power Supply Ripple Rejection
4.3.4 Efficiency of Low Dropout Linear Regulator
Table 2. LDO regulator efficiency
4.4 Simulation Results and Analysis
Figure 4-18. Transient response
Figure 4-19. Switching-LDO building block
Figure 4-22. Switching-LDO tree design waveforms
Figure 4-23. Switching-LDO tree design quiescent waveforms
Figure 4-25. Switching-LDO tree design
Figure 4-26. Switching-LDO parallel design waveforms
Table 3. LDO regulator efficiency, parallel design
5 FUTURE WORK
5.1 Power Management and Thermal Stability in Multi-Core Chips
Figure 5-1. Multi-core/multi-block Dynamic Power Management System
5.2 Efficient Power Gating Techniques for Multi-Core Design
Figure 5-2. The Proposed Power Gating Scheme
Figure 5-3. Switching regulator operating with transconductance gyrator
6 CONCLUSION
REFERENCES
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Juliana MS THESIS Final

Juliana MS THESIS Final

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Published by Hans Ransijn

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Published by: Hans Ransijn on Jul 21, 2011
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11/25/2012

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