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rr222201-switching-theory-and-logic-design

rr222201-switching-theory-and-logic-design

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Published by: SRINIVASA RAO GANTA on Sep 18, 2008
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Code No: RR222201
Set No. 1
II B.Tech Supplimentary Examinations, Aug/Sep 2008SWITCHING THEORY AND LOGIC DESIGN(Instrumentation & Control Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆⋆⋆⋆⋆
1. (a) Consider the following four codes.Code A Code B Code C Code D0001 000 01011 0000000010 001 01100 0011110100 2 011 1 10010 3 110011 41000 010 10101110111101100Which of the following properties is satisfied by each of the above codes?i. Detects single errorsii. Detects double errorsiii. Detects triple errorsiv. Corrects single errorsv. Corrects double errorsCorrects singe and detects double errors.(b) Add the following decimal number 109 and 876 in BCD and Excess-3 forms.[8+8]2. (a) Simplify the function using Karnaugh map methodF (A,B,C,D) =
(4,5,7,12,14,15)+
d(3,8,10).(b) Give three possible ways to express the functionF =
A B D
+
A B C D
+
ABD
+
ABCD
with eight or less literals. [8+8]3. (a) Derive Boolean expression for a 2input Ex-OR gate to realize with 2 inputNAND gates without using complemented variables and draw the circuit.(b) Redraw the given circuit in (gure3b)after simplication. [8+8]Figure 3b1 of 2
 
Code No: RR222201
Set No. 1
4. (a) Give the circuit implementation of a 4 - bit carry look-ahead adder.(b) Give the implementation of a 2 -bit magnitude comparator.(c) Bring out the dierences among a PAL and PLA. [6+6+4]5. (a) What is the race around condition in flip-flops. Explain with the help of example.(b) Give transition tables for the given flop-flops J-K, R-S, T and D-Flip-Flops(c) Draw the circuit of positive edge trigger J-K flip-flop with active high presetand active low clear and explain its operation with the help of Truth-Table.[6+4+6]6. Design a synchronous modulo 10 up down counter .Use T flip flops for synthesis.[16]7. Find the equivalence partition and a corresponding reduced machine in standardform. [16]PS NS, 2X=0 X=1A B,0 E,0B E,0 D,0C D,1 A,0D C,1 E,0E B,0 D,0F C,1 C,1G C,1 D,1H C,0 A,18. (a) Construct an ASM chart for a decimal system that counts the number of people in a room. People enter the room from one door, with a photocell thatchanges a signal x from 1 to 0, when the light is interpreted. They leave theroom from a second door, with a similar photocell with a signal y. Both x andy are synchronized with a clock but they may stay on or off for more thanone clock pulse period. The data processor subsystem consists of an up downcounter with a display of its contents.(b) Design a four bit counter with synchronous clear with a diagram specified inthe data processor [8+8]
⋆⋆⋆⋆⋆
2 of 2
 
Code No: RR222201
Set No. 2
II B.Tech Supplimentary Examinations, Aug/Sep 2008SWITCHING THEORY AND LOGIC DESIGN(Instrumentation & Control Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆⋆⋆⋆⋆
1. (a) A person on SATURN possessing 18 fingers has a property worth (1,00,000)
18
.He has 3 daughters and two sons. He wants to distribute half the moneyequally to his sons and the remaining half to his daughters equally. Howmuch his each son and each daughter will get in Indian currency?(b) An Indian started on an expedition to SATURN with Rs.1,00,000. The expen-diture on SATURN will be in the ratio of 1:2:7 for food, clothing and traveling.How much he will be spending on each item in the currency of SATURN.[8+8]2. (a) Simplify the Boolean function F using the don?t care conditions d, ini. sum of products andii. product of sums where
=
A B D
+
ACD
+
ABC and d
=
ABCD
+
ACD
+
A B D
(b) F(A, B, C, D) =
π
max [5, 8, 14] + d[7, 11, 12, 13, 15]. Obtain minimal sopfunction. [8+8]3. (a) Implement the following Boolen function F together with the don?t care con-ditions D using not more than two NOR gates. Assume that both normal andcomplement inputs are available.
(
A,B,C,D
) =
(0.1.2.9,11)
D
(
A,B,C,D
) =
(8,10,14,15)(b) What are universal gates. Why they are so called. Give their truth tables.[12+4]4. (a) Design 64 line output demultiplexer using lower order demultiplexer. Such as4 to 16 and 2 to 4 Demultiplexers.(b) Give the NAND gate realization of full-adder. [10+6]5. (a) Define a latch. Draw the schematic circuit of D-Latch using NAND gates andexplain its operations.(b) Draw the schematic circuit of J-K Master-slove Flip-Flop with active low clearand preset inputs and explain its operation with the help of Truth-Table [8+8]6. Design a clocked sequential circuit to detect 1111 or 0000 and it will produce anoutput z=1 at the end of sequence. Overlapping is allowed. Draw the circuit usingD ip ops. [16]1 of 2

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