Code No: RR222201 Set No.

1
II B.Tech Supplimentary Examinations, Aug/Sep 2008
SWITCHING THEORY AND LOGIC DESIGN
(Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Consider the following four codes.

Code A Code B Code C Code D

0001 000 01011 000000
0010 001 01100 001111
0100 2 011 1 10010 3 110011 4
1000 010 10101
110
111
101
100

Which of the following properties is satisfied by each of the above codes?

i. Detects single errors
ii. Detects double errors
iii. Detects triple errors
iv. Corrects single errors
v. Corrects double errors
Corrects singe and detects double errors.
(b) Add the following decimal number 109 and 876 in BCD and Excess-3 forms.
[8+8]

2. (a) Simplify the function

P using Karnaugh
Pmap method
F (A,B,C,D) = (4,5,7,12,14,15)+ d(3,8,10).
(b) Give three possible ways to express the function
F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]

3. (a) Derive Boolean expression for a 2input Ex-OR gate to realize with 2 input
NAND gates without using complemented variables and draw the circuit.
(b) Redraw the given circuit in (figure3b)after simplification. [8+8]

Figure 3b

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Code No: RR222201 Set No. 1
4. (a) Give the circuit implementation of a 4 - bit carry look-ahead adder.
(b) Give the implementation of a 2 -bit magnitude comparator.
(c) Bring out the differences among a PAL and PLA. [6+6+4]

5. (a) What is the race around condition in flip-flops. Explain with the help of
example.
(b) Give transition tables for the given flop-flops J-K, R-S, T and D-Flip-Flops
(c) Draw the circuit of positive edge trigger J-K flip-flop with active high preset
and active low clear and explain its operation with the help of Truth-Table.
[6+4+6]

6. Design a synchronous modulo 10 up down counter .Use T flip flops for synthesis.
[16]

7. Find the equivalence partition and a corresponding reduced machine in standard

form. [16]

PS NS, 2
X=0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0
F C,1 C,1
G C,1 D,1
H C,0 A,1

8. (a) Construct an ASM chart for a decimal system that counts the number of
people in a room. People enter the room from one door, with a photocell that
changes a signal x from 1 to 0, when the light is interpreted. They leave the
room from a second door, with a similar photocell with a signal y. Both x and
y are synchronized with a clock but they may stay on or off for more than
one clock pulse period. The data processor subsystem consists of an up down
counter with a display of its contents.
(b) Design a four bit counter with synchronous clear with a diagram specified in
the data processor [8+8]

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Code No: RR222201 Set No. 2
II B.Tech Supplimentary Examinations, Aug/Sep 2008
SWITCHING THEORY AND LOGIC DESIGN
(Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) A person on SATURN possessing 18 fingers has a property worth (1,00,000)18 .

He has 3 daughters and two sons. He wants to distribute half the money
equally to his sons and the remaining half to his daughters equally. How
much his each son and each daughter will get in Indian currency?
(b) An Indian started on an expedition to SATURN with Rs.1,00,000. The expen-
diture on SATURN will be in the ratio of 1:2:7 for food, clothing and traveling.
How much he will be spending on each item in the currency of SATURN.[8+8]

2. (a) Simplify the Boolean function F using the don?t care conditions d, in
i. sum of products and
ii. product of sums where
F = A B D + ACD + ABC and d = ABCD + ACD + A B D
(b) F(A, B, C, D) = π max [5, 8, 14] + d[7, 11, 12, 13, 15]. Obtain minimal sop
function. [8+8]

3. (a) Implement the following Boolen function F together with the don?t care con-
ditions D using not more than two NOR gates. Assume that both normal and
complement inputs are available.
P
F (A, B, C, D) = P(0.1.2.9,11)
D(A, B, C, D) = (8,10,14,15)
(b) What are universal gates. Why they are so called. Give their truth tables.
[12+4]

4. (a) Design 64 line output demultiplexer using lower order demultiplexer. Such as
4 to 16 and 2 to 4 Demultiplexers.
(b) Give the NAND gate realization of full-adder. [10+6]

5. (a) Define a latch. Draw the schematic circuit of D-Latch using NAND gates and
explain its operations.
(b) Draw the schematic circuit of J-K Master-slove Flip-Flop with active low clear
and preset inputs and explain its operation with the help of Truth-Table [8+8]

6. Design a clocked sequential circuit to detect 1111 or 0000 and it will produce an
output z=1 at the end of sequence. Overlapping is allowed. Draw the circuit using
D flip flops. [16]

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Code No: RR222201 Set No. 2
7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]

PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1

8. Draw the ASM chart of binary multiplier and design the control circuit using each
of the following methods :-

(a) JK flip flop and gates

(b) D flip flop and decoder [8+8]

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Code No: RR222201 Set No. 3
II B.Tech Supplimentary Examinations, Aug/Sep 2008
SWITCHING THEORY AND LOGIC DESIGN
(Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) i. Express decimal digits 0-9 in BCD code and 2-4-2-1 code.
ii. Determine which of the above codes are self complementing.
(b) i. Convert the decimal number 96 into binary and convert it to gray code
number.
ii. Convert the given gray code number to binary: 1001001011. [8+8]

2. Four persons, members of a TV panel game, each have an ON/OFF button that is
used to record their opinion of a certain pop record. Instead of recording individual
scores, some data processing is required such that the score board shows a HIT when
the majority vote is in favour of and a MISS if it is against Provision must also be
made for a TIE. From this verbal statement.

(a) Derive the truth tables separately for HIT, MISS and TIE.
(b) Extract S-O-P and P-O-S for each of the three outputs.
(c) Simplify the equation in SOP form. [6+6+4]

3. Use tabular procedure

P to simplify the given expression
f(v,w,x,y,z) = m(0,4,12,16,19,24,27,28,29,31) in SOP form and draw the circuit
using only NAND gates. [16]

4. Implement the following functions using a PROM

P
(a) F(w,x,y,z) = (1,9,12,15)
P
(b) G(w,x,y,z)= (0,1,2,3,4,5,7,8,10,11,12,13,14,15) [8+8]

5. (a) What is the race around condition in flip-flops. Explain with the help of
example.
(b) Give transition tables for the given flop-flops J-K, R-S, T and D-Flip-Flops
(c) Draw the circuit of positive edge trigger J-K flip-flop with active high preset
and active low clear and explain its operation with the help of Truth-Table.
[6+4+6]

6. (a) Compare merits and demerits of ripple and synchronous counters.

(b) Design a modulo-12 up synchronous counter using T-flip flops and draw the
circuit diagram. [6+10]

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Code No: RR222201 Set No. 3
7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]

PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1

8. (a) Explain in detail the block diagram of ASM chart.

(b) Draw the portion of an ASM chart that specifies the conditional operation to
increment register R during state T1 and transfer to state T2, if control inputs
z and y are = 1 and 0 respectively. [8+8]

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Code No: RR222201 Set No. 4
II B.Tech Supplimentary Examinations, Aug/Sep 2008
SWITCHING THEORY AND LOGIC DESIGN
(Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Write the following binary numbers in signed 1’s complement form and signed
2’s complement form using 16 bit registers.
i. +1001010
ii. -11110000
iii. -11001100.1
iv. +100000011.111
(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s
complement representation. Verify your answers by using decimal addition
and subtraction
i. N1=00110010, N2=11111101
ii. N1=10001110, N2=00001101. [10+6]

2. (a) With the use of maps find the simplest form in sum of products of the function
F =fg. where f and g are given by
f = wxy + yz + wyz + xyz
g = (w + x + y z)(x + y + z)(w + y + z)
(b) Obtain the simplified expression in POS (product of sums) of F(w,x,y,z)
=π(1,3,5,7,13,15)+d(6, 12, 14) [8+8]

3. Implement the function F with the following two level forms

(a) NAND-AND,
(b) AND-NOR,
(c) OR-NAND and
(d) NOR-OR P
F (A, B, C, D) = (0,1,2,3,4,8,9,12) [16]

4. (a) Give the circuit implementation of a 4 - bit carry look-ahead adder.

(b) Give the implementation of a 2 -bit magnitude comparator.
(c) Bring out the differences among a PAL and PLA. [6+6+4]

5. (a) Give the transition tables for the following flip-flops

i. T-Flip-Flop
ii. R-S flip-flop

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Code No: RR222201 Set No. 4
(b) Draw the schematic circuit of J-K-Flip-Flop with negative edge triggering.
Convert this flip-flop to Toggle flip-flop (T). Give its truth-table, Justify the
entries in the truth-table [6+10]

6. Design a 4-bit universal shift register and draw the circuit with the given mode of
operation table. [16]
S1 S0 Operation
0 0 Parallel
0 1 Shift right
1 0 Shift left
1 1 Inhibit clock

7. (a) Distinguish between Mealy and Moore machines

(b) Convert the following Mealy machine into a corresponding Moore machine:
[6+10]

PS NS,Z
X-0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0

8. Design a half adder and half subtractor circuit using

(a) multiplexer and registers

(b) one flipflop per state. Draw the state diagram and convert it to ASM block
and tablulate its state table. [8+8]

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