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Section 18. USART

Section 18. USART

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Published by Guillermo Hernandez

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Published by: Guillermo Hernandez on Jul 26, 2011
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11/01/2013

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PICmicro MID-RANGE MCU FAMILY
DS31018A-page 18-2
©
1997 Microchip Technology Inc.
18.1 Introduction
 
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of thetwo serial I/O modules (other is the SSP module). The USART is also known as a Serial Com-munications Interface or SCI. The USART can be configured as a full duplex asynchronous sys-tem that can communicate with peripheral devices such as CRT terminals and personalcomputers, or it can be configured as a half duplex synchronous system that can communicatewith peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.The USART can be configured in the following modes:Asynchronous (full duplex)Synchronous - Master (half duplex)Synchronous - Slave (half duplex)The SPEN bit (RCSTA<7>), and the TRIS bits, have to be set in order to configure the TX/CK andRX/DT pins for the USART.
 
©
1997 Microchip Technology Inc.DS31018A-page 18-3
Section 18. USART
 U  S 
18
18.2 Control Registers
Register 18-1:TXSTA: Transmit Status and Control Register
R/W-0R/W-0R/W-0R/W-0U-0R/W-0R-1R/W-0CSRCTX9TXENSYNCBRGHTRMTTX9Dbit 7bit 0bit 7
CSRC:
Clock Source Select bitAsynchronous modeDon’t careSynchronous mode1 = Master mode (Clock generated internally from BRG)0 = Slave mode (Clock from external source)bit 6
TX9
: 9-bit Transmit Enable bit1 = Selects 9-bit transmission0 = Selects 8-bit transmissionbit 5
TXEN
: Transmit Enable bit1 = Transmit enabled0 = Transmit disabled
Note:
SREN/CREN overrides TXEN in SYNC mode.bit 4
SYNC
: USART Mode Select bit1 = Synchronous mode0 = Asynchronous modebit 3
Unimplemented:
Read as '0'bit 2
BRGH
: High Baud Rate Select bitAsynchronous mode1 = High speed0 = Low speedSynchronous modeUnused in this modebit 1
TRMT
: Transmit Shift Register Status bit1 = TSR empty0 = TSR fullbit 0
TX9D:
9th bit of transmit data. Can be parity bit.LegendR = Readable bitW = Writable bitU = Unimplemented bit, read as 0- n = Value at POR reset

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